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Wysocki" , Len Brown , Thomas Gleixner , Marc Zyngier , Daniel Lezcano , Jonathan Corbet , Anup Patel , Atish Patra , 'Conor Dooley ' , "Rafael J . Wysocki" Subject: Re: [PATCH V3 12/20] RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap() Message-ID: References: <20230303133647.845095-1-sunilvl@ventanamicro.com> <20230303133647.845095-13-sunilvl@ventanamicro.com> <20230303161647.mksonnutzaw4d3gb@orel> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230303161647.mksonnutzaw4d3gb@orel> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230303_095525_456222_5098A64E X-CRM114-Status: GOOD ( 19.13 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, Mar 03, 2023 at 05:16:47PM +0100, Andrew Jones wrote: > On Fri, Mar 03, 2023 at 07:06:39PM +0530, Sunil V L wrote: > > On ACPI based systems, the information about the hart > > like ISA is provided by the RISC-V Hart Capabilities Table (RHCT). > > Enable filling up hwcap structure based on the information in RHCT. > > > > Signed-off-by: Sunil V L > > Acked-by: Rafael J. Wysocki > > --- > > arch/riscv/kernel/cpufeature.c | 41 ++++++++++++++++++++++++++-------- > > 1 file changed, 32 insertions(+), 9 deletions(-) > > > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > > index 59d58ee0f68d..478dbf129922 100644 > > --- a/arch/riscv/kernel/cpufeature.c > > +++ b/arch/riscv/kernel/cpufeature.c > > @@ -6,6 +6,7 @@ > > * Copyright (C) 2017 SiFive > > */ > > > > +#include > > #include > > #include > > #include > > @@ -13,6 +14,8 @@ > > #include > > #include > > #include > > +#include > > +#include > > #include > > #include > > #include > > @@ -91,7 +94,9 @@ void __init riscv_fill_hwcap(void) > > char print_str[NUM_ALPHA_EXTS + 1]; > > int i, j, rc; > > unsigned long isa2hwcap[26] = {0}; > > - unsigned long hartid; > > + struct acpi_table_header *rhct; > > + acpi_status status; > > + unsigned int cpu; > > > > isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I; > > isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M; > > @@ -104,18 +109,33 @@ void __init riscv_fill_hwcap(void) > > > > bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX); > > > > - for_each_of_cpu_node(node) { > > + if (!acpi_disabled) { > > + status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct); > > + if (ACPI_FAILURE(status)) > > + return; > > + } > > + > > + for_each_possible_cpu(cpu) { > > unsigned long this_hwcap = 0; > > DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); > > const char *temp; > > > > - rc = riscv_of_processor_hartid(node, &hartid); > > - if (rc < 0) > > - continue; > > The above is an unrelated cleanup and should be in a separate patch. > Okay, let me split this. Thanks, Sunil _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv