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Wysocki" , Nathan Chancellor , Thomas Gleixner , Maximilian Luz , "David S . Miller" , Len Brown Subject: Re: [PATCH V4 23/23] crypto: hisilicon/qm: Workaround to enable build with RISC-V clang Message-ID: References: <20230404182037.863533-1-sunilvl@ventanamicro.com> <20230404182037.863533-24-sunilvl@ventanamicro.com> <20230404-viewpoint-shank-674a8940809a@spud> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230404-viewpoint-shank-674a8940809a@spud> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230405_034645_067593_32E88D27 X-CRM114-Status: GOOD ( 23.42 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hi Conor, On Tue, Apr 04, 2023 at 10:59:41PM +0100, Conor Dooley wrote: > Hey Sunil, > > This one made me scratch my head for a bit.. > > On Tue, Apr 04, 2023 at 11:50:37PM +0530, Sunil V L wrote: > > With CONFIG_ACPI enabled for RISC-V, this driver gets enabled in > > allmodconfig build. The gcc tool chain builds this driver removing the > > inline arm64 assembly code. However, clang for RISC-V tries to build > > the arm64 assembly and below error is seen. > > There's actually nothing RISC-V specific about that behaviour, that's > just how clang works. Quoting Nathan: > "Clang performs semantic analysis (i.e., validates assembly) before > dead code elimination, so IS_ENABLED() is not sufficient for avoiding > that error." > Huh, It never occurred to me that this issue could be known already since I always thought we are hitting this first time since ACPI is enabled only now for RISC-V. Thank you very much!. > > drivers/crypto/hisilicon/qm.c:627:10: error: invalid output constraint '+Q' in asm > > "+Q" (*((char __iomem *)fun_base)) > > ^ > > It appears that RISC-V clang is not smart enough to detect > > IS_ENABLED(CONFIG_ARM64) and remove the dead code. > > So I think this statement is just not true, it can remove dead code, but > only after it has done the semantic analysis. > Yes, with more details now, let me update the commit message. > The reason that this has not been seen before, again quoting Nathan, is: > "arm64 and x86_64 both support the Q constraint, we cannot build > LoongArch yet (although it does not have support for Q either so same > boat as RISC-V), and ia64 is dead/unsupported in LLVM. Those are the > only architectures that support ACPI, so I guess that explains why we > have seen no issues aside from RISC-V so far." > > > As a workaround, move this check to preprocessing stage which works > > with the RISC-V clang tool chain. > > I don't think there's much else you can do! > Reviewed-by: Conor Dooley > > Perhaps it is also worth adding: > Link: https://github.com/ClangBuiltLinux/linux/issues/999 > Sure, Thank you very much for digging this! Thanks, Sunil _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv