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Received: from [2a01:e34:ec5d:a741:8a4c:7c4e:dc4c:1787] (helo=ohm.rr44.fr) by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1qFiXA-00F8ep-Bi; Sat, 01 Jul 2023 23:53:36 +0200 Received: from aurel32 by ohm.rr44.fr with local (Exim 4.96) (envelope-from ) id 1qFiX8-00FDHi-1D; Sat, 01 Jul 2023 23:53:34 +0200 Date: Sat, 1 Jul 2023 23:53:34 +0200 From: Aurelien Jarno To: jiajie.ho@starfivetech.com Cc: Palmer Dabbelt , olivia@selenic.com, herbert@gondor.apana.org.au, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, kernel@esmil.dk, Conor Dooley , linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH v5 3/3] riscv: dts: starfive: Add TRNG node for VisionFive 2 Message-ID: Mail-Followup-To: jiajie.ho@starfivetech.com, Palmer Dabbelt , olivia@selenic.com, herbert@gondor.apana.org.au, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, kernel@esmil.dk, Conor Dooley , linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org References: <20230117015445.32500-4-jiajie.ho@starfivetech.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/2.2.9 (2022-11-12) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230701_145427_774481_C4500ECD X-CRM114-Status: GOOD ( 12.82 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 2023-03-14 18:45, Palmer Dabbelt wrote: > On Mon, 16 Jan 2023 17:54:45 PST (-0800), jiajie.ho@starfivetech.com wrote: > > Adding StarFive TRNG controller node to VisionFive 2 SoC. > > > > Co-developed-by: Jenny Zhang > > Signed-off-by: Jenny Zhang > > Signed-off-by: Jia Jie Ho > > --- > > arch/riscv/boot/dts/starfive/jh7110.dtsi | 10 ++++++++++ > > 1 file changed, 10 insertions(+) > > > > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi > > index 4ac159d79d66..3c29e0bc6246 100644 > > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi > > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi > > @@ -455,5 +455,15 @@ uart5: serial@12020000 { > > reg-shift = <2>; > > status = "disabled"; > > }; > > + > > + rng: rng@1600c000 { > > + compatible = "starfive,jh7110-trng"; > > + reg = <0x0 0x1600C000 0x0 0x4000>; > > + clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>, > > + <&stgcrg JH7110_STGCLK_SEC_MISCAHB>; > > + clock-names = "hclk", "ahb"; > > + resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>; > > + interrupts = <30>; > > + }; > > }; > > }; > > Acked-by: Palmer Dabbelt It appears that this patch has never been applied, although the rest of the series has already been merged. Unfortunately it doesn't apply anymore due to other changes to that file. Could you please rebase and resend it? -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://aurel32.net _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv