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Thu, 27 Jul 2023 17:11:10 -0700 (PDT) Received: from x1 ([2601:1c2:1800:f680:dacb:3a1a:fcaf:c0fc]) by smtp.gmail.com with ESMTPSA id l16-20020a170902f69000b001b8a3729c23sm2230932plg.17.2023.07.27.17.11.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jul 2023 17:11:10 -0700 (PDT) Date: Thu, 27 Jul 2023 17:11:08 -0700 From: Drew Fustini To: Xi Ruoyao Cc: Jisheng Zhang , Conor Dooley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano , Guo Ren , Fu Wei , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support Message-ID: References: <20230617161529.2092-1-jszhang@kernel.org> <20230725-unheard-dingy-42f0fafe7216@wendy> <3e0994dab495920ac590dc28d6b9d9765abe0c7e.camel@linuxfromscratch.org> <866eab3e30a18c50742a75d62aee223fdc7e3cee.camel@linuxfromscratch.org> <4986b92f1a5aa303a529c6004aaedd2184c3ccf7.camel@linuxfromscratch.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <4986b92f1a5aa303a529c6004aaedd2184c3ccf7.camel@linuxfromscratch.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230727_171114_695169_F2C5BF38 X-CRM114-Status: GOOD ( 18.42 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, Jul 27, 2023 at 08:54:59AM +0800, Xi Ruoyao wrote: > On Thu, 2023-07-27 at 08:14 +0800, Xi Ruoyao wrote: > > On Wed, 2023-07-26 at 23:00 +0800, Jisheng Zhang wrote: > > > which dts r u using? see below. > > > = > > > > = > > > > Or maybe my toolchain (GCC 13.1.0, Binutils-2.40, with no patches) = can > > > > miscompile the kernel? > > = > > /* snip */ > > = > > > > Boot HART ID=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 : 0 > > > > Boot HART Domain=A0=A0=A0=A0=A0=A0=A0=A0=A0 : root > > > > Boot HART Priv Version=A0=A0=A0 : v1.11 > > > > Boot HART Base ISA=A0=A0=A0=A0=A0=A0=A0 : rv64imafdcvx > > > = > > > what? I don't think the mainline dts provide v and x. = > > = > > I copied the compiled arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dtb > > into /boot and loaded it with u-boot "load" command onto 0x46000000, and > > passed this address to the booti command. > > = > > But maybe I've copied the wrong file or made some other mistake... I'll > > recheck. > = > Hmm, and if I read OpenSBI code correctly, this line reflects the > content of the misa CSR, not the DT riscv,isa value. > = > The log of successful boot provided by Drew also contains > "rv64imafdcvx": > = > https://gist.github.com/pdp7/23259595a7570f1f11086d286e16dfb6 In case it helps, the thead fork of u-boot contains an important file include/configs/light-c910.h that defines the boot scripts for each board. Here is the BeagleV Ahead: https://git.beagleboard.org/beaglev-ahead/beaglev-ahead-u-boot/-/blob/beagl= ev-v2020.01-1.1.2/include/configs/light-c910.h#L361 It might give some clues as to want commands to try. >From the lpi4a config: https://github.com/revyos/thead-u-boot/blob/09e2c3f93f1a64c10ca51d9b9c0c22f= bc0947c43/configs/light_lpi4a_defconfig It looks like it sets: CONFIG_TARGET_LIGHT_FM_C910_LPI4A=3Dy And that corresponds to: https://github.com/revyos/thead-u-boot/blob/09e2c3f93f1a64c10ca51d9b9c0c22f= bc0947c43/include/configs/light-c910.h#L425 Anyways, I finally got my Lichee Pi 4a out of the box, and I am going to try it out too. -Drew _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv