From: Drew Fustini <dfustini@baylibre.com>
To: Xi Ruoyao <xry111@linuxfromscratch.org>
Cc: Jisheng Zhang <jszhang@kernel.org>,
Conor Dooley <conor.dooley@microchip.com>,
Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Guo Ren <guoren@kernel.org>, Fu Wei <wefu@redhat.com>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support
Date: Fri, 28 Jul 2023 00:04:46 -0700 [thread overview]
Message-ID: <ZMNojqwLxcG8FcHN@x1> (raw)
In-Reply-To: <290101d386866f639a7c482527d7a78c5108d49b.camel@linuxfromscratch.org>
On Fri, Jul 28, 2023 at 12:29:44AM +0800, Xi Ruoyao wrote:
> On Fri, 2023-07-28 at 00:11 +0800, Jisheng Zhang wrote:
> > On Thu, Jul 27, 2023 at 08:54:59AM +0800, Xi Ruoyao wrote:
> > > On Thu, 2023-07-27 at 08:14 +0800, Xi Ruoyao wrote:
> > > > On Wed, 2023-07-26 at 23:00 +0800, Jisheng Zhang wrote:
> > > > > which dts r u using? see below.
> > > > >
> > > > > >
> > > > > > Or maybe my toolchain (GCC 13.1.0, Binutils-2.40, with no
> > > > > > patches) can
> > > > > > miscompile the kernel?
> > > >
> > > > /* snip */
> > > >
> > > > > > Boot HART ID : 0
> > > > > > Boot HART Domain : root
> > > > > > Boot HART Priv Version : v1.11
> > > > > > Boot HART Base ISA : rv64imafdcvx
> > > > >
> > > > > what? I don't think the mainline dts provide v and x.
> > > >
> > > > I copied the compiled arch/riscv/boot/dts/thead/th1520-lichee-pi-
> > > > 4a.dtb
> > > > into /boot and loaded it with u-boot "load" command onto
> > > > 0x46000000, and
> > > > passed this address to the booti command.
> > > >
> > > > But maybe I've copied the wrong file or made some other mistake...
> > > > I'll
> > > > recheck.
> > >
> > > Hmm, and if I read OpenSBI code correctly, this line reflects the
> > > content of the misa CSR, not the DT riscv,isa value.
> > >
> >
> > Aha indeed the "vx" isa extensions are not from the DT riscv,isa
> > property. I will try your opensbi/linux/uboot combinations on my
> > lpi4a board tomorrow.
>
> My kernel config attached. Maybe you can find some stupid mistake in
> it, I'm not familiar with RISC-V, nor DT-based systems :(.
It seems like your kernel config is the problem. I used it and I saw
the same result of a panic in riscv_intc_irq:
https://gist.github.com/pdp7/1a26ebe20017a3b90c4e9c005f8178e1
This is the config I have been using successfully:
https://gist.github.com/pdp7/ecb34ba1e93fc6cfc4dce66d71e14f82
Could you try that config?
Linux 6.5-rc3 boots okay when built with it:
https://gist.github.com/pdp7/580b072f9a5bf9be87cf88b5f81e50e3
Thanks,
Drew
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next prev parent reply other threads:[~2023-07-28 7:05 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-17 16:15 [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 1/8] dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 2/8] dt-bindings: timer: Add T-HEAD TH1520 clint Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 3/8] dt-bindings: riscv: Add T-HEAD TH1520 board compatibles Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 4/8] riscv: Add the T-HEAD SoC family Kconfig option Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 5/8] riscv: dts: add initial T-HEAD TH1520 SoC device tree Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 6/8] riscv: dts: thead: add sipeed Lichee Pi 4A board " Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 7/8] MAINTAINERS: add entry for T-HEAD RISC-V SoC Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 8/8] riscv: defconfig: enable T-HEAD SoC Jisheng Zhang
2023-06-17 17:02 ` [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support Conor Dooley
2023-06-18 16:14 ` Jisheng Zhang
2023-06-17 18:20 ` Conor Dooley
2023-06-18 16:25 ` Jisheng Zhang
2023-06-18 21:01 ` Conor Dooley
2023-06-20 22:52 ` Conor Dooley
2023-06-20 22:55 ` Conor Dooley
2023-07-25 7:38 ` Xi Ruoyao
2023-07-25 7:52 ` Conor Dooley
2023-07-25 8:10 ` Conor Dooley
2023-07-25 14:32 ` Drew Fustini
2023-07-25 8:26 ` Xi Ruoyao
2023-07-25 14:58 ` Jisheng Zhang
2023-07-26 12:48 ` Xi Ruoyao
2023-07-26 15:00 ` Jisheng Zhang
2023-07-27 0:14 ` Xi Ruoyao
2023-07-27 0:54 ` Xi Ruoyao
2023-07-27 9:18 ` Xi Ruoyao
2023-07-27 16:11 ` Jisheng Zhang
2023-07-27 16:29 ` Xi Ruoyao
2023-07-28 7:04 ` Drew Fustini [this message]
2023-07-28 7:40 ` Xi Ruoyao
2023-07-28 10:05 ` Xi Ruoyao
2023-07-28 10:23 ` Emil Renner Berthing
2023-07-28 17:53 ` Drew Fustini
2023-07-29 7:11 ` Xi Ruoyao
2023-07-28 0:11 ` Drew Fustini
2023-08-11 17:39 ` Drew Fustini
2023-08-11 17:46 ` Conor Dooley
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