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Fri, 28 Jul 2023 00:04:48 -0700 (PDT) Received: from x1 ([2601:1c2:1800:f680:dacb:3a1a:fcaf:c0fc]) by smtp.gmail.com with ESMTPSA id o14-20020a170902d4ce00b001bb750189desm2778063plg.255.2023.07.28.00.04.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Jul 2023 00:04:48 -0700 (PDT) Date: Fri, 28 Jul 2023 00:04:46 -0700 From: Drew Fustini To: Xi Ruoyao Cc: Jisheng Zhang , Conor Dooley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano , Guo Ren , Fu Wei , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support Message-ID: References: <20230617161529.2092-1-jszhang@kernel.org> <20230725-unheard-dingy-42f0fafe7216@wendy> <3e0994dab495920ac590dc28d6b9d9765abe0c7e.camel@linuxfromscratch.org> <866eab3e30a18c50742a75d62aee223fdc7e3cee.camel@linuxfromscratch.org> <4986b92f1a5aa303a529c6004aaedd2184c3ccf7.camel@linuxfromscratch.org> <290101d386866f639a7c482527d7a78c5108d49b.camel@linuxfromscratch.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <290101d386866f639a7c482527d7a78c5108d49b.camel@linuxfromscratch.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230728_000451_560934_DCB9A4B4 X-CRM114-Status: GOOD ( 21.81 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, Jul 28, 2023 at 12:29:44AM +0800, Xi Ruoyao wrote: > On Fri, 2023-07-28 at 00:11 +0800, Jisheng Zhang wrote: > > On Thu, Jul 27, 2023 at 08:54:59AM +0800, Xi Ruoyao wrote: > > > On Thu, 2023-07-27 at 08:14 +0800, Xi Ruoyao wrote: > > > > On Wed, 2023-07-26 at 23:00 +0800, Jisheng Zhang wrote: > > > > > which dts r u using? see below. > > > > > = > > > > > > = > > > > > > Or maybe my toolchain (GCC 13.1.0, Binutils-2.40, with no > > > > > > patches) can > > > > > > miscompile the kernel? > > > > = > > > > /* snip */ > > > > = > > > > > > Boot HART ID=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 : 0 > > > > > > Boot HART Domain=A0=A0=A0=A0=A0=A0=A0=A0=A0 : root > > > > > > Boot HART Priv Version=A0=A0=A0 : v1.11 > > > > > > Boot HART Base ISA=A0=A0=A0=A0=A0=A0=A0 : rv64imafdcvx > > > > > = > > > > > what? I don't think the mainline dts provide v and x. = > > > > = > > > > I copied the compiled arch/riscv/boot/dts/thead/th1520-lichee-pi- > > > > 4a.dtb > > > > into /boot and loaded it with u-boot "load" command onto > > > > 0x46000000, and > > > > passed this address to the booti command. > > > > = > > > > But maybe I've copied the wrong file or made some other mistake... > > > > I'll > > > > recheck. > > > = > > > Hmm, and if I read OpenSBI code correctly, this line reflects the > > > content of the misa CSR, not the DT riscv,isa value. > > > = > > = > > Aha indeed the "vx" isa extensions are not from the DT riscv,isa > > property. I will try your opensbi/linux/uboot combinations on my > > lpi4a board tomorrow. > = > My kernel config attached. Maybe you can find some stupid mistake in > it, I'm not familiar with RISC-V, nor DT-based systems :(. It seems like your kernel config is the problem. I used it and I saw the same result of a panic in riscv_intc_irq: https://gist.github.com/pdp7/1a26ebe20017a3b90c4e9c005f8178e1 This is the config I have been using successfully: https://gist.github.com/pdp7/ecb34ba1e93fc6cfc4dce66d71e14f82 Could you try that config? Linux 6.5-rc3 boots okay when built with it: https://gist.github.com/pdp7/580b072f9a5bf9be87cf88b5f81e50e3 Thanks, Drew _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv