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b=EiWKqKNEx0rlUi0TYT1DzAMNNR74ylyO4JQRIT+fYrw5aFgXzaEbhwFmWpNp/xeBA ijXUQlrPLZ7udmp2wr54axnH4xbejIhvTDiX3alzUIg6lRy2G6gqAFHmQ/7E0L7XP9 7NfG1xBcVfPrppm3vpGvmF2xwOne2NtMKaZBfDiH+y4e+EIj3CSOt/bbmOCu7BbIrA Pkoig5Bwth6iYxOoyeCaunQF9fNmkvRmQhZjUvv1q4Z0W6CrZshYCSH0LhgfhsTStf d56zuQ/TzgSEtH39vsWx5w3Qj+iYRw4p4wu4p4xFH0woVTmcOTVkG92m+qPrYc8+Ia IJmrjWnr4V2jQ== Date: Thu, 3 Aug 2023 03:33:59 -0400 From: Guo Ren To: Leonardo Bras Cc: Will Deacon , Peter Zijlstra , Boqun Feng , Mark Rutland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Andrzej Hajda , Arnd Bergmann , Ingo Molnar , Palmer Dabbelt , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [RFC PATCH v2 3/3] riscv/atomic.h : Deduplicate arch_atomic.* Message-ID: References: <20230803051401.710236-2-leobras@redhat.com> <20230803051401.710236-5-leobras@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230803051401.710236-5-leobras@redhat.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230803_003413_407084_33575270 X-CRM114-Status: GOOD ( 18.97 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, Aug 03, 2023 at 02:14:00AM -0300, Leonardo Bras wrote: > Some functions use mostly the same asm for 32-bit and 64-bit versions. > > Make a macro that is generic enough and avoid code duplication. > > (This did not cause any change in generated asm) > > Signed-off-by: Leonardo Bras > --- > arch/riscv/include/asm/atomic.h | 164 +++++++++++++++----------------- > 1 file changed, 76 insertions(+), 88 deletions(-) > > diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h > index f5dfef6c2153..80cca7ac16fd 100644 > --- a/arch/riscv/include/asm/atomic.h > +++ b/arch/riscv/include/asm/atomic.h > @@ -196,22 +196,28 @@ ATOMIC_OPS(xor, xor, i) > #undef ATOMIC_FETCH_OP > #undef ATOMIC_OP_RETURN > > +#define _arch_atomic_fetch_add_unless(_prev, _rc, counter, _a, _u, sfx) \ > +({ \ > + __asm__ __volatile__ ( \ > + "0: lr." sfx " %[p], %[c]\n" \ > + " beq %[p], %[u], 1f\n" \ > + " add %[rc], %[p], %[a]\n" \ > + " sc." sfx ".rl %[rc], %[rc], %[c]\n" \ > + " bnez %[rc], 0b\n" \ > + " fence rw, rw\n" \ > + "1:\n" \ > + : [p]"=&r" (_prev), [rc]"=&r" (_rc), [c]"+A" (counter) \ > + : [a]"r" (_a), [u]"r" (_u) \ > + : "memory"); \ > +}) > + > /* This is required to provide a full barrier on success. */ > static __always_inline int arch_atomic_fetch_add_unless(atomic_t *v, int a, int u) > { > int prev, rc; > > - __asm__ __volatile__ ( > - "0: lr.w %[p], %[c]\n" > - " beq %[p], %[u], 1f\n" > - " add %[rc], %[p], %[a]\n" > - " sc.w.rl %[rc], %[rc], %[c]\n" > - " bnez %[rc], 0b\n" > - " fence rw, rw\n" > - "1:\n" > - : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) > - : [a]"r" (a), [u]"r" (u) > - : "memory"); > + _arch_atomic_fetch_add_unless(prev, rc, v->counter, a, u, "w"); > + > return prev; > } > #define arch_atomic_fetch_add_unless arch_atomic_fetch_add_unless > @@ -222,77 +228,86 @@ static __always_inline s64 arch_atomic64_fetch_add_unless(atomic64_t *v, s64 a, > s64 prev; > long rc; > > - __asm__ __volatile__ ( > - "0: lr.d %[p], %[c]\n" > - " beq %[p], %[u], 1f\n" > - " add %[rc], %[p], %[a]\n" > - " sc.d.rl %[rc], %[rc], %[c]\n" > - " bnez %[rc], 0b\n" > - " fence rw, rw\n" > - "1:\n" > - : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) > - : [a]"r" (a), [u]"r" (u) > - : "memory"); > + _arch_atomic_fetch_add_unless(prev, rc, v->counter, a, u, "d"); > + > return prev; > } > #define arch_atomic64_fetch_add_unless arch_atomic64_fetch_add_unless > #endif > > +#define _arch_atomic_inc_unless_negative(_prev, _rc, counter, sfx) \ > +({ \ > + __asm__ __volatile__ ( \ > + "0: lr." sfx " %[p], %[c]\n" \ > + " bltz %[p], 1f\n" \ > + " addi %[rc], %[p], 1\n" \ > + " sc." sfx ".rl %[rc], %[rc], %[c]\n" \ > + " bnez %[rc], 0b\n" \ > + " fence rw, rw\n" \ > + "1:\n" \ > + : [p]"=&r" (_prev), [rc]"=&r" (_rc), [c]"+A" (counter) \ > + : \ > + : "memory"); \ > +}) > + > static __always_inline bool arch_atomic_inc_unless_negative(atomic_t *v) > { > int prev, rc; > > - __asm__ __volatile__ ( > - "0: lr.w %[p], %[c]\n" > - " bltz %[p], 1f\n" > - " addi %[rc], %[p], 1\n" > - " sc.w.rl %[rc], %[rc], %[c]\n" > - " bnez %[rc], 0b\n" > - " fence rw, rw\n" > - "1:\n" > - : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) > - : > - : "memory"); > + _arch_atomic_inc_unless_negative(prev, rc, v->counter, "w"); > + > return !(prev < 0); > } > > #define arch_atomic_inc_unless_negative arch_atomic_inc_unless_negative > > +#define _arch_atomic_dec_unless_positive(_prev, _rc, counter, sfx) \ > +({ \ > + __asm__ __volatile__ ( \ > + "0: lr." sfx " %[p], %[c]\n" \ > + " bgtz %[p], 1f\n" \ > + " addi %[rc], %[p], -1\n" \ > + " sc." sfx ".rl %[rc], %[rc], %[c]\n" \ > + " bnez %[rc], 0b\n" \ > + " fence rw, rw\n" \ > + "1:\n" \ > + : [p]"=&r" (_prev), [rc]"=&r" (_rc), [c]"+A" (counter) \ > + : \ > + : "memory"); \ > +}) > + > static __always_inline bool arch_atomic_dec_unless_positive(atomic_t *v) > { > int prev, rc; > > - __asm__ __volatile__ ( > - "0: lr.w %[p], %[c]\n" > - " bgtz %[p], 1f\n" > - " addi %[rc], %[p], -1\n" > - " sc.w.rl %[rc], %[rc], %[c]\n" > - " bnez %[rc], 0b\n" > - " fence rw, rw\n" > - "1:\n" > - : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) > - : > - : "memory"); > + _arch_atomic_dec_unless_positive(prev, rc, v->counter, "w"); > + > return !(prev > 0); > } > > #define arch_atomic_dec_unless_positive arch_atomic_dec_unless_positive > > +#define _arch_atomic_dec_if_positive(_prev, _rc, counter, sfx) \ > +({ \ > + __asm__ __volatile__ ( \ > + "0: lr." sfx " %[p], %[c]\n" \ > + " addi %[rc], %[p], -1\n" \ > + " bltz %[rc], 1f\n" \ > + " sc." sfx ".rl %[rc], %[rc], %[c]\n" \ > + " bnez %[rc], 0b\n" \ > + " fence rw, rw\n" \ > + "1:\n" \ > + : [p]"=&r" (_prev), [rc]"=&r" (_rc), [c]"+A" (counter) \ > + : \ > + : "memory"); \ > +}) > + > static __always_inline int arch_atomic_dec_if_positive(atomic_t *v) > { > int prev, rc; > > - __asm__ __volatile__ ( > - "0: lr.w %[p], %[c]\n" > - " addi %[rc], %[p], -1\n" > - " bltz %[rc], 1f\n" > - " sc.w.rl %[rc], %[rc], %[c]\n" > - " bnez %[rc], 0b\n" > - " fence rw, rw\n" > - "1:\n" > - : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) > - : > - : "memory"); > + _arch_atomic_dec_if_positive(prev, rc, v->counter, "w"); > + > return prev - 1; > } > > @@ -304,17 +319,8 @@ static __always_inline bool arch_atomic64_inc_unless_negative(atomic64_t *v) > s64 prev; > long rc; > > - __asm__ __volatile__ ( > - "0: lr.d %[p], %[c]\n" > - " bltz %[p], 1f\n" > - " addi %[rc], %[p], 1\n" > - " sc.d.rl %[rc], %[rc], %[c]\n" > - " bnez %[rc], 0b\n" > - " fence rw, rw\n" > - "1:\n" > - : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) > - : > - : "memory"); > + _arch_atomic_inc_unless_negative(prev, rc, v->counter, "d"); > + > return !(prev < 0); > } > > @@ -325,17 +331,8 @@ static __always_inline bool arch_atomic64_dec_unless_positive(atomic64_t *v) > s64 prev; > long rc; > > - __asm__ __volatile__ ( > - "0: lr.d %[p], %[c]\n" > - " bgtz %[p], 1f\n" > - " addi %[rc], %[p], -1\n" > - " sc.d.rl %[rc], %[rc], %[c]\n" > - " bnez %[rc], 0b\n" > - " fence rw, rw\n" > - "1:\n" > - : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) > - : > - : "memory"); > + _arch_atomic_dec_unless_positive(prev, rc, v->counter, "d"); > + > return !(prev > 0); > } > > @@ -346,17 +343,8 @@ static __always_inline s64 arch_atomic64_dec_if_positive(atomic64_t *v) > s64 prev; > long rc; > > - __asm__ __volatile__ ( > - "0: lr.d %[p], %[c]\n" > - " addi %[rc], %[p], -1\n" > - " bltz %[rc], 1f\n" > - " sc.d.rl %[rc], %[rc], %[c]\n" > - " bnez %[rc], 0b\n" > - " fence rw, rw\n" > - "1:\n" > - : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) > - : > - : "memory"); > + _arch_atomic_dec_if_positive(prev, rc, v->counter, "d"); > + > return prev - 1; > } I have no problem with this optimization. Reviewed-by: Guo Ren > > -- > 2.41.0 > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv