* [PATCH v2 1/2] riscv: errata: fix T-Head dcache.cva encoding
2023-08-27 9:08 [PATCH v2 0/2] riscv: errata: improve T-Head CMO Jisheng Zhang
@ 2023-08-27 9:08 ` Jisheng Zhang
2023-09-04 19:43 ` Drew Fustini
2023-08-27 9:08 ` [PATCH v2 2/2] riscv: errata: prefix T-Head mnemonics with th Jisheng Zhang
` (3 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: Jisheng Zhang @ 2023-08-27 9:08 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren
Cc: Sergey Matyukevich, linux-riscv, Heiko Stuebner, linux-kernel
From: Icenowy Zheng <uwu@icenowy.me>
The dcache.cva encoding shown in the comments are wrong, it's for
dcache.cval1 (which is restricted to L1) instead.
Fix this in the comment and in the hardcoded instruction.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Tested-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Guo Ren <guoren@kernel.org>
---
arch/riscv/include/asm/errata_list.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index fb1a810f3d8c..feab334dd832 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -100,7 +100,7 @@ asm volatile(ALTERNATIVE( \
* | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
* 0000001 01001 rs1 000 00000 0001011
* dcache.cva rs1 (clean, virtual address)
- * 0000001 00100 rs1 000 00000 0001011
+ * 0000001 00101 rs1 000 00000 0001011
*
* dcache.cipa rs1 (clean then invalidate, physical address)
* | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
@@ -113,7 +113,7 @@ asm volatile(ALTERNATIVE( \
* 0000000 11001 00000 000 00000 0001011
*/
#define THEAD_inval_A0 ".long 0x0265000b"
-#define THEAD_clean_A0 ".long 0x0245000b"
+#define THEAD_clean_A0 ".long 0x0255000b"
#define THEAD_flush_A0 ".long 0x0275000b"
#define THEAD_SYNC_S ".long 0x0190000b"
--
2.40.1
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^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v2 1/2] riscv: errata: fix T-Head dcache.cva encoding
2023-08-27 9:08 ` [PATCH v2 1/2] riscv: errata: fix T-Head dcache.cva encoding Jisheng Zhang
@ 2023-09-04 19:43 ` Drew Fustini
2023-09-04 19:59 ` Drew Fustini
0 siblings, 1 reply; 9+ messages in thread
From: Drew Fustini @ 2023-09-04 19:43 UTC (permalink / raw)
To: Jisheng Zhang
Cc: Sergey Matyukevich, Albert Ou, linux-kernel, Guo Ren,
Paul Walmsley, Palmer Dabbelt, linux-riscv, Heiko Stuebner
On Sun, Aug 27, 2023 at 05:08:12PM +0800, Jisheng Zhang wrote:
> From: Icenowy Zheng <uwu@icenowy.me>
>
> The dcache.cva encoding shown in the comments are wrong, it's for
> dcache.cval1 (which is restricted to L1) instead.
>
> Fix this in the comment and in the hardcoded instruction.
>
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> Tested-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> Reviewed-by: Guo Ren <guoren@kernel.org>
> ---
> arch/riscv/include/asm/errata_list.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> index fb1a810f3d8c..feab334dd832 100644
> --- a/arch/riscv/include/asm/errata_list.h
> +++ b/arch/riscv/include/asm/errata_list.h
> @@ -100,7 +100,7 @@ asm volatile(ALTERNATIVE( \
> * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> * 0000001 01001 rs1 000 00000 0001011
> * dcache.cva rs1 (clean, virtual address)
> - * 0000001 00100 rs1 000 00000 0001011
> + * 0000001 00101 rs1 000 00000 0001011
> *
> * dcache.cipa rs1 (clean then invalidate, physical address)
> * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> @@ -113,7 +113,7 @@ asm volatile(ALTERNATIVE( \
> * 0000000 11001 00000 000 00000 0001011
> */
> #define THEAD_inval_A0 ".long 0x0265000b"
> -#define THEAD_clean_A0 ".long 0x0245000b"
> +#define THEAD_clean_A0 ".long 0x0255000b"
> #define THEAD_flush_A0 ".long 0x0275000b"
> #define THEAD_SYNC_S ".long 0x0190000b"
>
> --
> 2.40.1
>
Tested-by: Drew Fustini <dfustini@baylibre.com>
I applied this on top of the emmc series [1] and the dma-noncoherent dts
patch [2]. SDMA is now working with this patch applied. Before this
patch, the filesystems on the emmc were corrupted after mounting. It
makes sense that problem is solved by the correct cache clean
instruction being used.
Thanks,
Drew
[1] https://lore.kernel.org/linux-riscv/20230724-th1520-emmc-v2-0-132ed2e2171e@baylibre.com/
[2] https://lore.kernel.org/linux-riscv/ZOIBQI3L4kP7c%2FT1@xhacker/
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/2] riscv: errata: fix T-Head dcache.cva encoding
2023-09-04 19:43 ` Drew Fustini
@ 2023-09-04 19:59 ` Drew Fustini
0 siblings, 0 replies; 9+ messages in thread
From: Drew Fustini @ 2023-09-04 19:59 UTC (permalink / raw)
To: Jisheng Zhang
Cc: Sergey Matyukevich, Albert Ou, linux-kernel, Guo Ren,
Paul Walmsley, Palmer Dabbelt, linux-riscv, Heiko Stuebner
On Mon, Sep 04, 2023 at 12:43:25PM -0700, Drew Fustini wrote:
> On Sun, Aug 27, 2023 at 05:08:12PM +0800, Jisheng Zhang wrote:
> > From: Icenowy Zheng <uwu@icenowy.me>
> >
> > The dcache.cva encoding shown in the comments are wrong, it's for
> > dcache.cval1 (which is restricted to L1) instead.
> >
> > Fix this in the comment and in the hardcoded instruction.
> >
> > Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> > Tested-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
> > Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> > Reviewed-by: Guo Ren <guoren@kernel.org>
> > ---
> > arch/riscv/include/asm/errata_list.h | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> > index fb1a810f3d8c..feab334dd832 100644
> > --- a/arch/riscv/include/asm/errata_list.h
> > +++ b/arch/riscv/include/asm/errata_list.h
> > @@ -100,7 +100,7 @@ asm volatile(ALTERNATIVE( \
> > * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> > * 0000001 01001 rs1 000 00000 0001011
> > * dcache.cva rs1 (clean, virtual address)
> > - * 0000001 00100 rs1 000 00000 0001011
> > + * 0000001 00101 rs1 000 00000 0001011
> > *
> > * dcache.cipa rs1 (clean then invalidate, physical address)
> > * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> > @@ -113,7 +113,7 @@ asm volatile(ALTERNATIVE( \
> > * 0000000 11001 00000 000 00000 0001011
> > */
> > #define THEAD_inval_A0 ".long 0x0265000b"
> > -#define THEAD_clean_A0 ".long 0x0245000b"
> > +#define THEAD_clean_A0 ".long 0x0255000b"
> > #define THEAD_flush_A0 ".long 0x0275000b"
> > #define THEAD_SYNC_S ".long 0x0190000b"
> >
> > --
> > 2.40.1
> >
>
> Tested-by: Drew Fustini <dfustini@baylibre.com>
>
> I applied this on top of the emmc series [1] and the dma-noncoherent dts
> patch [2]. SDMA is now working with this patch applied. Before this
> patch, the filesystems on the emmc were corrupted after mounting. It
> makes sense that problem is solved by the correct cache clean
> instruction being used.
Even better, ADMA is now working in sdhci-of-dwcmshc too.
I'll respin my eMMC series.
Thanks,
Drew
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^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 2/2] riscv: errata: prefix T-Head mnemonics with th.
2023-08-27 9:08 [PATCH v2 0/2] riscv: errata: improve T-Head CMO Jisheng Zhang
2023-08-27 9:08 ` [PATCH v2 1/2] riscv: errata: fix T-Head dcache.cva encoding Jisheng Zhang
@ 2023-08-27 9:08 ` Jisheng Zhang
2023-08-27 10:18 ` Guo Ren
2023-08-27 11:21 ` [PATCH v2 0/2] riscv: errata: improve T-Head CMO Jisheng Zhang
` (2 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: Jisheng Zhang @ 2023-08-27 9:08 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren
Cc: linux-riscv, linux-kernel
From: Icenowy Zheng <uwu@icenowy.me>
T-Head now maintains some specification for their extended instructions
at [1], in which all instructions are prefixed "th.".
Follow this practice in the kernel comments.
Link: https://github.com/T-head-Semi/thead-extension-spec [1]
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
---
arch/riscv/include/asm/errata_list.h | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index feab334dd832..98ecab053dd2 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -90,25 +90,25 @@ asm volatile(ALTERNATIVE( \
#endif
/*
- * dcache.ipa rs1 (invalidate, physical address)
+ * th.dcache.ipa rs1 (invalidate, physical address)
* | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
* 0000001 01010 rs1 000 00000 0001011
- * dache.iva rs1 (invalida, virtual address)
+ * th.dache.iva rs1 (invalida, virtual address)
* 0000001 00110 rs1 000 00000 0001011
*
- * dcache.cpa rs1 (clean, physical address)
+ * th.dcache.cpa rs1 (clean, physical address)
* | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
* 0000001 01001 rs1 000 00000 0001011
- * dcache.cva rs1 (clean, virtual address)
+ * th.dcache.cva rs1 (clean, virtual address)
* 0000001 00101 rs1 000 00000 0001011
*
- * dcache.cipa rs1 (clean then invalidate, physical address)
+ * th.dcache.cipa rs1 (clean then invalidate, physical address)
* | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
* 0000001 01011 rs1 000 00000 0001011
- * dcache.civa rs1 (... virtual address)
+ * th.dcache.civa rs1 (... virtual address)
* 0000001 00111 rs1 000 00000 0001011
*
- * sync.s (make sure all cache operations finished)
+ * th.sync.s (make sure all cache operations finished)
* | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
* 0000000 11001 00000 000 00000 0001011
*/
--
2.40.1
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^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v2 2/2] riscv: errata: prefix T-Head mnemonics with th.
2023-08-27 9:08 ` [PATCH v2 2/2] riscv: errata: prefix T-Head mnemonics with th Jisheng Zhang
@ 2023-08-27 10:18 ` Guo Ren
0 siblings, 0 replies; 9+ messages in thread
From: Guo Ren @ 2023-08-27 10:18 UTC (permalink / raw)
To: Jisheng Zhang
Cc: Albert Ou, linux-kernel, Palmer Dabbelt, Paul Walmsley,
linux-riscv
On Sun, Aug 27, 2023 at 5:20 AM Jisheng Zhang <jszhang@kernel.org> wrote:
>
> From: Icenowy Zheng <uwu@icenowy.me>
>
> T-Head now maintains some specification for their extended instructions
> at [1], in which all instructions are prefixed "th.".
>
> Follow this practice in the kernel comments.
>
> Link: https://github.com/T-head-Semi/thead-extension-spec [1]
> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> ---
> arch/riscv/include/asm/errata_list.h | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> index feab334dd832..98ecab053dd2 100644
> --- a/arch/riscv/include/asm/errata_list.h
> +++ b/arch/riscv/include/asm/errata_list.h
> @@ -90,25 +90,25 @@ asm volatile(ALTERNATIVE( \
> #endif
>
> /*
> - * dcache.ipa rs1 (invalidate, physical address)
> + * th.dcache.ipa rs1 (invalidate, physical address)
> * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> * 0000001 01010 rs1 000 00000 0001011
> - * dache.iva rs1 (invalida, virtual address)
> + * th.dache.iva rs1 (invalida, virtual address)
> * 0000001 00110 rs1 000 00000 0001011
> *
> - * dcache.cpa rs1 (clean, physical address)
> + * th.dcache.cpa rs1 (clean, physical address)
> * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> * 0000001 01001 rs1 000 00000 0001011
> - * dcache.cva rs1 (clean, virtual address)
> + * th.dcache.cva rs1 (clean, virtual address)
> * 0000001 00101 rs1 000 00000 0001011
> *
> - * dcache.cipa rs1 (clean then invalidate, physical address)
> + * th.dcache.cipa rs1 (clean then invalidate, physical address)
> * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> * 0000001 01011 rs1 000 00000 0001011
> - * dcache.civa rs1 (... virtual address)
> + * th.dcache.civa rs1 (... virtual address)
> * 0000001 00111 rs1 000 00000 0001011
> *
> - * sync.s (make sure all cache operations finished)
> + * th.sync.s (make sure all cache operations finished)
Reviewed-by: Guo Ren <guoren@kernel.org>
> * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> * 0000000 11001 00000 000 00000 0001011
> */
> --
> 2.40.1
>
--
Best Regards
Guo Ren
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 0/2] riscv: errata: improve T-Head CMO
2023-08-27 9:08 [PATCH v2 0/2] riscv: errata: improve T-Head CMO Jisheng Zhang
2023-08-27 9:08 ` [PATCH v2 1/2] riscv: errata: fix T-Head dcache.cva encoding Jisheng Zhang
2023-08-27 9:08 ` [PATCH v2 2/2] riscv: errata: prefix T-Head mnemonics with th Jisheng Zhang
@ 2023-08-27 11:21 ` Jisheng Zhang
2023-09-13 0:37 ` patchwork-bot+linux-riscv
2023-11-02 20:20 ` patchwork-bot+linux-riscv
4 siblings, 0 replies; 9+ messages in thread
From: Jisheng Zhang @ 2023-08-27 11:21 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren
Cc: linux-riscv, linux-kernel
On Sun, Aug 27, 2023 at 05:08:11PM +0800, Jisheng Zhang wrote:
> This is a renew of Icenowy patch series[1], patch1 is necessary to
> make T-Head C910 powered SoCs CMO work correctly. patch2 is to name
> those instructions following thead-extension-spec.
Original series:
https://lore.kernel.org/linux-riscv/20230103062610.69704-1-uwu@icenowy.me/
>
> Icenowy Zheng (2):
> riscv: errata: fix T-Head dcache.cva encoding
> riscv: errata: prefix T-Head mnemonics with th.
>
> arch/riscv/include/asm/errata_list.h | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> --
> 2.40.1
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 0/2] riscv: errata: improve T-Head CMO
2023-08-27 9:08 [PATCH v2 0/2] riscv: errata: improve T-Head CMO Jisheng Zhang
` (2 preceding siblings ...)
2023-08-27 11:21 ` [PATCH v2 0/2] riscv: errata: improve T-Head CMO Jisheng Zhang
@ 2023-09-13 0:37 ` patchwork-bot+linux-riscv
2023-11-02 20:20 ` patchwork-bot+linux-riscv
4 siblings, 0 replies; 9+ messages in thread
From: patchwork-bot+linux-riscv @ 2023-09-13 0:37 UTC (permalink / raw)
To: Jisheng Zhang
Cc: linux-riscv, paul.walmsley, palmer, aou, guoren, linux-kernel
Hello:
This series was applied to riscv/linux.git (fixes)
by Palmer Dabbelt <palmer@rivosinc.com>:
On Sun, 27 Aug 2023 17:08:11 +0800 you wrote:
> This is a renew of Icenowy patch series[1], patch1 is necessary to
> make T-Head C910 powered SoCs CMO work correctly. patch2 is to name
> those instructions following thead-extension-spec.
>
> Icenowy Zheng (2):
> riscv: errata: fix T-Head dcache.cva encoding
> riscv: errata: prefix T-Head mnemonics with th.
>
> [...]
Here is the summary with links:
- [v2,1/2] riscv: errata: fix T-Head dcache.cva encoding
https://git.kernel.org/riscv/c/8eb8fe67e2c8
- [v2,2/2] riscv: errata: prefix T-Head mnemonics with th.
(no matching commit)
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
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^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH v2 0/2] riscv: errata: improve T-Head CMO
2023-08-27 9:08 [PATCH v2 0/2] riscv: errata: improve T-Head CMO Jisheng Zhang
` (3 preceding siblings ...)
2023-09-13 0:37 ` patchwork-bot+linux-riscv
@ 2023-11-02 20:20 ` patchwork-bot+linux-riscv
4 siblings, 0 replies; 9+ messages in thread
From: patchwork-bot+linux-riscv @ 2023-11-02 20:20 UTC (permalink / raw)
To: Jisheng Zhang
Cc: linux-riscv, paul.walmsley, palmer, aou, guoren, linux-kernel
Hello:
This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@rivosinc.com>:
On Sun, 27 Aug 2023 17:08:11 +0800 you wrote:
> This is a renew of Icenowy patch series[1], patch1 is necessary to
> make T-Head C910 powered SoCs CMO work correctly. patch2 is to name
> those instructions following thead-extension-spec.
>
> Icenowy Zheng (2):
> riscv: errata: fix T-Head dcache.cva encoding
> riscv: errata: prefix T-Head mnemonics with th.
>
> [...]
Here is the summary with links:
- [v2,1/2] riscv: errata: fix T-Head dcache.cva encoding
(no matching commit)
- [v2,2/2] riscv: errata: prefix T-Head mnemonics with th.
https://git.kernel.org/riscv/c/c1c99e5f1b13
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
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^ permalink raw reply [flat|nested] 9+ messages in thread