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From: Drew Fustini <dfustini@baylibre.com>
To: Jisheng Zhang <jszhang@kernel.org>
Cc: Sergey Matyukevich <sergey.matyukevich@syntacore.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	linux-kernel@vger.kernel.org, Guo Ren <guoren@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	linux-riscv@lists.infradead.org, Heiko Stuebner <heiko@sntech.de>
Subject: Re: [PATCH v2 1/2] riscv: errata: fix T-Head dcache.cva encoding
Date: Mon, 4 Sep 2023 12:59:02 -0700	[thread overview]
Message-ID: <ZPY3BpYMzs6FbrNS@x1> (raw)
In-Reply-To: <ZPYzXeYGyGCxJUuK@x1>

On Mon, Sep 04, 2023 at 12:43:25PM -0700, Drew Fustini wrote:
> On Sun, Aug 27, 2023 at 05:08:12PM +0800, Jisheng Zhang wrote:
> > From: Icenowy Zheng <uwu@icenowy.me>
> > 
> > The dcache.cva encoding shown in the comments are wrong, it's for
> > dcache.cval1 (which is restricted to L1) instead.
> > 
> > Fix this in the comment and in the hardcoded instruction.
> > 
> > Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
> > Tested-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
> > Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> > Reviewed-by: Guo Ren <guoren@kernel.org>
> > ---
> >  arch/riscv/include/asm/errata_list.h | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> > index fb1a810f3d8c..feab334dd832 100644
> > --- a/arch/riscv/include/asm/errata_list.h
> > +++ b/arch/riscv/include/asm/errata_list.h
> > @@ -100,7 +100,7 @@ asm volatile(ALTERNATIVE(						\
> >   * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> >   *   0000001    01001      rs1       000      00000  0001011
> >   * dcache.cva rs1 (clean, virtual address)
> > - *   0000001    00100      rs1       000      00000  0001011
> > + *   0000001    00101      rs1       000      00000  0001011
> >   *
> >   * dcache.cipa rs1 (clean then invalidate, physical address)
> >   * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> > @@ -113,7 +113,7 @@ asm volatile(ALTERNATIVE(						\
> >   *   0000000    11001     00000      000      00000  0001011
> >   */
> >  #define THEAD_inval_A0	".long 0x0265000b"
> > -#define THEAD_clean_A0	".long 0x0245000b"
> > +#define THEAD_clean_A0	".long 0x0255000b"
> >  #define THEAD_flush_A0	".long 0x0275000b"
> >  #define THEAD_SYNC_S	".long 0x0190000b"
> >  
> > -- 
> > 2.40.1
> > 
> 
> Tested-by: Drew Fustini <dfustini@baylibre.com>
> 
> I applied this on top of the emmc series [1] and the dma-noncoherent dts
> patch [2]. SDMA is now working with this patch applied. Before this
> patch, the filesystems on the emmc were corrupted after mounting. It
> makes sense that problem is solved by the correct cache clean
> instruction being used.

Even better, ADMA is now working in sdhci-of-dwcmshc too.

I'll respin my eMMC series.

Thanks,
Drew

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  reply	other threads:[~2023-09-04 19:59 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-27  9:08 [PATCH v2 0/2] riscv: errata: improve T-Head CMO Jisheng Zhang
2023-08-27  9:08 ` [PATCH v2 1/2] riscv: errata: fix T-Head dcache.cva encoding Jisheng Zhang
2023-09-04 19:43   ` Drew Fustini
2023-09-04 19:59     ` Drew Fustini [this message]
2023-08-27  9:08 ` [PATCH v2 2/2] riscv: errata: prefix T-Head mnemonics with th Jisheng Zhang
2023-08-27 10:18   ` Guo Ren
2023-08-27 11:21 ` [PATCH v2 0/2] riscv: errata: improve T-Head CMO Jisheng Zhang
2023-09-13  0:37 ` patchwork-bot+linux-riscv
2023-11-02 20:20 ` patchwork-bot+linux-riscv

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