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Mon, 04 Sep 2023 12:59:04 -0700 (PDT) Date: Mon, 4 Sep 2023 12:59:02 -0700 From: Drew Fustini To: Jisheng Zhang Subject: Re: [PATCH v2 1/2] riscv: errata: fix T-Head dcache.cva encoding Message-ID: References: <20230827090813.1353-1-jszhang@kernel.org> <20230827090813.1353-2-jszhang@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230904_125909_671359_D4EE596B X-CRM114-Status: GOOD ( 24.06 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sergey Matyukevich , Albert Ou , linux-kernel@vger.kernel.org, Guo Ren , Paul Walmsley , Palmer Dabbelt , linux-riscv@lists.infradead.org, Heiko Stuebner Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Sep 04, 2023 at 12:43:25PM -0700, Drew Fustini wrote: > On Sun, Aug 27, 2023 at 05:08:12PM +0800, Jisheng Zhang wrote: > > From: Icenowy Zheng > > > > The dcache.cva encoding shown in the comments are wrong, it's for > > dcache.cval1 (which is restricted to L1) instead. > > > > Fix this in the comment and in the hardcoded instruction. > > > > Signed-off-by: Icenowy Zheng > > Tested-by: Sergey Matyukevich > > Reviewed-by: Heiko Stuebner > > Reviewed-by: Guo Ren > > --- > > arch/riscv/include/asm/errata_list.h | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h > > index fb1a810f3d8c..feab334dd832 100644 > > --- a/arch/riscv/include/asm/errata_list.h > > +++ b/arch/riscv/include/asm/errata_list.h > > @@ -100,7 +100,7 @@ asm volatile(ALTERNATIVE( \ > > * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | > > * 0000001 01001 rs1 000 00000 0001011 > > * dcache.cva rs1 (clean, virtual address) > > - * 0000001 00100 rs1 000 00000 0001011 > > + * 0000001 00101 rs1 000 00000 0001011 > > * > > * dcache.cipa rs1 (clean then invalidate, physical address) > > * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | > > @@ -113,7 +113,7 @@ asm volatile(ALTERNATIVE( \ > > * 0000000 11001 00000 000 00000 0001011 > > */ > > #define THEAD_inval_A0 ".long 0x0265000b" > > -#define THEAD_clean_A0 ".long 0x0245000b" > > +#define THEAD_clean_A0 ".long 0x0255000b" > > #define THEAD_flush_A0 ".long 0x0275000b" > > #define THEAD_SYNC_S ".long 0x0190000b" > > > > -- > > 2.40.1 > > > > Tested-by: Drew Fustini > > I applied this on top of the emmc series [1] and the dma-noncoherent dts > patch [2]. SDMA is now working with this patch applied. Before this > patch, the filesystems on the emmc were corrupted after mounting. It > makes sense that problem is solved by the correct cache clean > instruction being used. Even better, ADMA is now working in sdhci-of-dwcmshc too. I'll respin my eMMC series. Thanks, Drew _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv