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Mon, 04 Sep 2023 13:22:33 -0700 (PDT) Date: Mon, 4 Sep 2023 13:22:32 -0700 From: Drew Fustini To: Jisheng Zhang Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Guo Ren , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] riscv: mm: update T-Head memory type definitions Message-ID: References: <20230827090644.1318-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230827090644.1318-1-jszhang@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230904_132235_467968_6BBBB0A3 X-CRM114-Status: GOOD ( 16.75 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Sun, Aug 27, 2023 at 05:06:44PM +0800, Jisheng Zhang wrote: > Update T-Head memory type definitions according to C910 doc [1] > For NC and IO, SH property isn't configurable, hardcoded as SH, > so set SH for NOCACHE and IO. > > And also set bit[61](Bufferable) for NOCACHE according to the > table 6.1 in the doc [1]. > > Link: https://github.com/T-head-Semi/openc910 [1] > Signed-off-by: Jisheng Zhang > --- > arch/riscv/include/asm/pgtable-64.h | 14 +++++++++----- > 1 file changed, 9 insertions(+), 5 deletions(-) > > diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h > index 7a5097202e15..9a2c780a11e9 100644 > --- a/arch/riscv/include/asm/pgtable-64.h > +++ b/arch/riscv/include/asm/pgtable-64.h > @@ -126,14 +126,18 @@ enum napot_cont_order { > > /* > * [63:59] T-Head Memory Type definitions: > - * > - * 00000 - NC Weakly-ordered, Non-cacheable, Non-bufferable, Non-shareable, Non-trustable > + * bit[63] SO - Strong Order > + * bit[62] C - Cacheable > + * bit[61] B - Bufferable > + * bit[60] SH - Shareable > + * bit[59] Sec - Trustable > + * 00110 - NC Weakly-ordered, Non-cacheable, Bufferable, Shareable, Non-trustable > * 01110 - PMA Weakly-ordered, Cacheable, Bufferable, Shareable, Non-trustable > - * 10000 - IO Strongly-ordered, Non-cacheable, Non-bufferable, Non-shareable, Non-trustable > + * 10010 - IO Strongly-ordered, Non-cacheable, Non-bufferable, Shareable, Non-trustable > */ > #define _PAGE_PMA_THEAD ((1UL << 62) | (1UL << 61) | (1UL << 60)) > -#define _PAGE_NOCACHE_THEAD 0UL > -#define _PAGE_IO_THEAD (1UL << 63) > +#define _PAGE_NOCACHE_THEAD ((1UL < 61) | (1UL << 60)) > +#define _PAGE_IO_THEAD ((1UL << 63) | (1UL << 60)) > #define _PAGE_MTMASK_THEAD (_PAGE_PMA_THEAD | _PAGE_IO_THEAD | (1UL << 59)) > > static inline u64 riscv_page_mtmask(void) > -- > 2.40.1 > Tested-by: Drew Fustini I applied this on top of: [1] riscv: errata: improve T-Head CMO [2] riscv: dts: thead: set dma-noncoherent to soc bus [3] RISC-V: Add basic eMMC support for BeagleV Ahead The BeagleV Ahead eMMC continues to function okay in ADMA mode after this patch was applied. Thanks, Drew [1] https://lore.kernel.org/linux-riscv/20230827090813.1353-1-jszhang@kernel.org/ [2] https://lore.kernel.org/linux-riscv/ZOIBQI3L4kP7c%2FT1@xhacker/ [3] https://lore.kernel.org/linux-riscv/20230724-th1520-emmc-v2-0-132ed2e2171e@baylibre.com/ _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv