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Thu, 07 Sep 2023 10:41:27 -0700 (PDT) Date: Thu, 7 Sep 2023 10:41:24 -0700 From: Charlie Jenkins To: Conor Dooley Subject: Re: [PATCH v2 3/5] riscv: Vector checksum header Message-ID: References: <20230905-optimize_checksum-v2-0-ccd658db743b@rivosinc.com> <20230905-optimize_checksum-v2-3-ccd658db743b@rivosinc.com> <20230907-6ed9570259e770b6a472ee61@fedora> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230907-6ed9570259e770b6a472ee61@fedora> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230907_104131_068427_91675D46 X-CRM114-Status: GOOD ( 25.10 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Albert Ou , linux-kernel@vger.kernel.org, Palmer Dabbelt , Paul Walmsley , linux-riscv@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, Sep 07, 2023 at 10:58:33AM +0100, Conor Dooley wrote: > On Tue, Sep 05, 2023 at 09:46:52PM -0700, Charlie Jenkins wrote: > > Vector code is written in assembly rather than using the GCC vector > > instrinsics because they did not provide optimal code. Vector > > instrinsic types are still used so the inline assembly can > > appropriately select vector registers. However, this code cannot be > > merged yet because it is currently not possible to use vector > > instrinsics in the kernel because vector support needs to be directly > > enabled by assembly. > > > > Signed-off-by: Charlie Jenkins > > --- > > arch/riscv/include/asm/checksum.h | 87 +++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 87 insertions(+) > > > > diff --git a/arch/riscv/include/asm/checksum.h b/arch/riscv/include/asm/checksum.h > > index 3f9d5a202e95..1d6c23cd1221 100644 > > --- a/arch/riscv/include/asm/checksum.h > > +++ b/arch/riscv/include/asm/checksum.h > > @@ -10,6 +10,10 @@ > > #include > > #include > > > > +#ifdef CONFIG_RISCV_ISA_V > > +#include > > +#endif > > + > > #ifdef CONFIG_32BIT > > typedef unsigned int csum_t; > > #else > > @@ -43,6 +47,89 @@ static inline __sum16 csum_fold(__wsum sum) > > */ > > static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl) > > { > > +#ifdef CONFIG_RISCV_ISA_V > > + if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) { > > + /* > > + * Vector is likely available when the kernel is compiled with > > + * vector support, so nop when vector is available and jump when > > + * vector is not available. > > + */ > > + asm_volatile_goto(ALTERNATIVE("j %l[no_vector]", "nop", 0, > > + RISCV_ISA_EXT_v, 1) > > + : > > + : > > + : > > + : no_vector); > > + } else { > > + if (!__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_v)) > > + goto no_vector; > > + } > > + > > + vuint64m1_t prev_buffer; > > + vuint32m1_t curr_buffer; > > + unsigned int vl; > > +#ifdef CONFIG_32_BIT > > + csum_t high_result, low_result; > > + > > + riscv_v_enable(); > > + asm(".option push \n\ > > + .option arch, +v \n\ > > + vsetivli x0, 1, e64, ta, ma \n\ > > Also, I don't see that you have addressed previous review comments from > Samuel: > https://lore.kernel.org/linux-riscv/0a8c98bf-46da-e77a-0431-a6c1e224af2e@sifive.com/ I added the check for vector as Samuel suggested, but then I accidentally used riscv_v_enable() instead of kernel_vector_begin(), I will make that change. - Charlie _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv