Re: [PATCH v2 3/5] riscv: Vector checksum header

From: Charlie Jenkins <charlie@rivosinc.com>
To: Conor Dooley <conor@kernel.org>
Cc: Albert Ou <aou@eecs.berkeley.edu>,
	linux-kernel@vger.kernel.org, Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	linux-riscv@lists.infradead.org
Subject: Re: [PATCH v2 3/5] riscv: Vector checksum header
Date: Thu, 7 Sep 2023 10:43:22 -0700	[thread overview]
Message-ID: <ZPoLuvJooH4W4IGA@ghost> (raw)
In-Reply-To: <20230907-c23868a1016a17299a470120@fedora>

On Thu, Sep 07, 2023 at 10:47:55AM +0100, Conor Dooley wrote:
> On Tue, Sep 05, 2023 at 09:46:52PM -0700, Charlie Jenkins wrote:
> > Vector code is written in assembly rather than using the GCC vector
> > instrinsics because they did not provide optimal code. Vector
> > instrinsic types are still used so the inline assembly can
> > appropriately select vector registers. However, this code cannot be
> > merged yet because it is currently not possible to use vector
> > instrinsics in the kernel because vector support needs to be directly
> > enabled by assembly.
> > 
> > Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
> > ---
> >  arch/riscv/include/asm/checksum.h | 87 +++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 87 insertions(+)
> > 
> > diff --git a/arch/riscv/include/asm/checksum.h b/arch/riscv/include/asm/checksum.h
> > index 3f9d5a202e95..1d6c23cd1221 100644
> > --- a/arch/riscv/include/asm/checksum.h
> > +++ b/arch/riscv/include/asm/checksum.h
> > @@ -10,6 +10,10 @@
> >  #include <linux/in6.h>
> >  #include <linux/uaccess.h>
> >  
> > +#ifdef CONFIG_RISCV_ISA_V
> > +#include <riscv_vector.h>
> > +#endif
> > +
> >  #ifdef CONFIG_32BIT
> >  typedef unsigned int csum_t;
> >  #else
> > @@ -43,6 +47,89 @@ static inline __sum16 csum_fold(__wsum sum)
> >   */
> >  static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
> >  {
> > +#ifdef CONFIG_RISCV_ISA_V
> > +	if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
> > +		/*
> > +		 * Vector is likely available when the kernel is compiled with
> > +		 * vector support, so nop when vector is available and jump when
> > +		 * vector is not available.
> > +		 */
> > +		asm_volatile_goto(ALTERNATIVE("j %l[no_vector]", "nop", 0,
> > +					      RISCV_ISA_EXT_v, 1)
> > +				  :
> > +				  :
> > +				  :
> > +				  : no_vector);
> > +	} else {
> > +		if (!__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_v))
> > +			goto no_vector;
> > +	}
> 
> Silly question maybe, but is this complexity required?
> If you were to go and do
> 	if (!has_vector())
> 		goto no_vector
> is there any meaningful difference difference in performance?
Yes I should use that instead.
> 
> 
> > +
> > +	vuint64m1_t prev_buffer;
> > +	vuint32m1_t curr_buffer;
> > +	unsigned int vl;
> > +#ifdef CONFIG_32_BIT
> > +	csum_t high_result, low_result;
> > +
> > +	riscv_v_enable();
> > +	asm(".option push						\n\
> > +	.option arch, +v						\n\
> > +	vsetivli x0, 1, e64, ta, ma					\n\
> > +	vmv.v.i %[prev_buffer], 0					\n\
> > +	1:								\n\
> > +	vsetvli %[vl], %[ihl], e32, m1, ta, ma				\n\
> > +	vle32.v %[curr_buffer], (%[iph])				\n\
> > +	vwredsumu.vs %[prev_buffer], %[curr_buffer], %[prev_buffer]	\n\
> > +	sub %[ihl], %[ihl], %[vl]					\n\
> > +	slli %[vl], %[vl], 2						\n\
> 
> Also, could you please try to align the operands for asm stuff?
> It makes quite a difference to readability.
> 
> Thanks,
> Conor.
> 
Will do.

- Charlie
> > +	add %[iph], %[vl], %[iph]					\n\
> > +	# If not all of iph could fit into vector reg, do another sum	\n\
> > +	bne %[ihl], zero, 1b						\n\
> > +	vsetivli x0, 1, e64, m1, ta, ma					\n\
> > +	vmv.x.s %[low_result], %[prev_buffer]				\n\
> > +	addi %[vl], x0, 32						\n\
> > +	vsrl.vx %[prev_buffer], %[prev_buffer], %[vl]			\n\
> > +	vmv.x.s %[high_result], %[prev_buffer]				\n\
> > +	.option pop"
> > +	: [vl] "=&r" (vl), [prev_buffer] "=&vd" (prev_buffer),
> > +		[curr_buffer] "=&vd" (curr_buffer),
> > +		[high_result] "=&r" (high_result),
> > +		[low_result] "=&r" (low_result)
> > +	: [iph] "r" (iph), [ihl] "r" (ihl));
> > +	riscv_v_disable();
> > +
> > +	high_result += low_result;
> > +	high_result += high_result < low_result;
> > +#else // !CONFIG_32_BIT
> > +	csum_t result;
> > +
> > +	riscv_v_enable();
> > +	asm(".option push						\n\
> > +	.option arch, +v						\n\
> > +	vsetivli x0, 1, e64, ta, ma					\n\
> > +	vmv.v.i %[prev_buffer], 0					\n\
> > +	1:								\n\
> > +	# Setup 32-bit sum of iph					\n\
> > +	vsetvli %[vl], %[ihl], e32, m1, ta, ma				\n\
> > +	vle32.v %[curr_buffer], (%[iph])				\n\
> > +	# Sum each 32-bit segment of iph that can fit into a vector reg	\n\
> > +	vwredsumu.vs %[prev_buffer], %[curr_buffer], %[prev_buffer]     \n\
> > +	subw %[ihl], %[ihl], %[vl]					\n\
> > +	slli %[vl], %[vl], 2						\n\
> > +	addw %[iph], %[vl], %[iph]					\n\
> > +	# If not all of iph could fit into vector reg, do another sum	\n\
> > +	bne %[ihl], zero, 1b						\n\
> > +	vsetvli x0, x0, e64, m1, ta, ma					\n\
> > +	vmv.x.s %[result], %[prev_buffer]				\n\
> > +	.option pop"
> > +	: [vl] "=&r" (vl), [prev_buffer] "=&vd" (prev_buffer),
> > +		[curr_buffer] "=&vd" (curr_buffer), [result] "=&r" (result)
> > +	: [iph] "r" (iph), [ihl] "r" (ihl));
> > +	riscv_v_disable();
> > +#endif // !CONFIG_32_BIT
> > +no_vector:
> > +#endif // !CONFIG_RISCV_ISA_V
> > +
> >  	csum_t csum = 0;
> >  	int pos = 0;
> >  
> > 
> > -- 
> > 2.42.0
> > 


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