[RFC 0/3] Add support for StarFive VisionFive 2 Lite board

[RFC 0/3] Add support for StarFive VisionFive 2 Lite board

[Hal Feng]

VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S industrial
SoC which can run at -40~85 degrees centigrade and up to 1.25GHz.

Board features:
- JH7110S SoC
- 2/4/8 GiB LPDDR4 DRAM
- AXP15060 PMIC
- 40 pin GPIO header
- 1x USB 3.0 host port
- 3x USB 2.0 host port
- 1x M.2 M-Key (size: 2242)
- 1x MicroSD slot (optional non-removable eMMC)
- 1x QSPI Flash
- 1x I2C EEPROM
- 1x 1Gbps Ethernet port
- SDIO-based Wi-Fi & UART-based Bluetooth
- 1x HDMI port
- 1x 2-lane DSI
- 1x 2-lane CSI

For more details, please see
https://www.kickstarter.com/projects/starfive/visionfive-2-lite-unlock-risc-v-sbc-at-199

Hal Feng (3):
  dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2 Lite
    board
  riscv: dts: starfive: jh7110-common: Move out some nodes to the board
    dts
  riscv: dts: starfive: Add VisionFive 2 Lite board device tree

 .../devicetree/bindings/riscv/starfive.yaml   |   5 +
 arch/riscv/boot/dts/starfive/Makefile         |   2 +
 .../boot/dts/starfive/jh7110-common.dtsi      |  22 ---
 .../jh7110-deepcomputing-fml13v01.dts         |  49 ++++++
 .../boot/dts/starfive/jh7110-milkv-mars.dts   |  49 ++++++
 .../dts/starfive/jh7110-pine64-star64.dts     |  49 ++++++
 .../jh7110-starfive-visionfive-2.dtsi         |  46 ++++++
 arch/riscv/boot/dts/starfive/jh7110.dtsi      |  16 --
 .../jh7110s-starfive-visionfive-2-lite.dts    | 152 ++++++++++++++++++
 9 files changed, 352 insertions(+), 38 deletions(-)
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dts


base-commit: 068a56e56fa81e42fc5f08dff34fab149bb60a09
-- 
2.43.2


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[RFC 1/3] dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2 Lite board

[Hal Feng]

Add device tree bindings for the StarFive JH7110S SoC
and the VisionFive 2 Lite board equipped with it.

JH7110S SoC is an industrial SoC which can run at -40~85 degrees centigrade
and up to 1.25GHz. Its CPU cores and peripherals are mostly similar to
those of the JH7110 SoC.

Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
 Documentation/devicetree/bindings/riscv/starfive.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml
index 7ef85174353d..a2952490709f 100644
--- a/Documentation/devicetree/bindings/riscv/starfive.yaml
+++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
@@ -33,6 +33,11 @@ properties:
               - starfive,visionfive-2-v1.3b
           - const: starfive,jh7110
 
+      - items:
+          - enum:
+              - starfive,visionfive-2-lite
+          - const: starfive,jh7110s
+
 additionalProperties: true
 
 ...
-- 
2.43.2


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[RFC 2/3] riscv: dts: starfive: jh7110-common: Move out some nodes to the board dts

[Hal Feng]

Some node in this file are not used by the upcoming VisionFive 2 Lite
board. Move them to the board dts to prepare for adding the new
VisionFive 2 Lite device tree.

Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
 .../boot/dts/starfive/jh7110-common.dtsi      | 22 ---------
 .../jh7110-deepcomputing-fml13v01.dts         | 49 +++++++++++++++++++
 .../boot/dts/starfive/jh7110-milkv-mars.dts   | 49 +++++++++++++++++++
 .../dts/starfive/jh7110-pine64-star64.dts     | 49 +++++++++++++++++++
 .../jh7110-starfive-visionfive-2.dtsi         | 46 +++++++++++++++++
 arch/riscv/boot/dts/starfive/jh7110.dtsi      | 16 ------
 6 files changed, 193 insertions(+), 38 deletions(-)

diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
index 2eaf01775ef5..8332622420ca 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
@@ -281,15 +281,9 @@ &mmc0 {
 	assigned-clock-rates = <50000000>;
 	bus-width = <8>;
 	bootph-pre-ram;
-	cap-mmc-highspeed;
-	mmc-ddr-1_8v;
-	mmc-hs200-1_8v;
-	cap-mmc-hw-reset;
 	post-power-on-delay-ms = <200>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc0_pins>;
-	vmmc-supply = <&vcc_3v3>;
-	vqmmc-supply = <&emmc_vdd>;
 	status = "okay";
 };
 
@@ -299,12 +293,7 @@ &mmc1 {
 	assigned-clock-rates = <50000000>;
 	bus-width = <4>;
 	bootph-pre-ram;
-	no-sdio;
-	no-mmc;
-	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
-	disable-wp;
 	cap-sd-highspeed;
-	post-power-on-delay-ms = <200>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc1_pins>;
 	status = "okay";
@@ -448,17 +437,6 @@ GPOEN_SYS_I2C6_DATA,
 	};
 
 	mmc0_pins: mmc0-0 {
-		 rst-pins {
-			pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
-					      GPOEN_ENABLE,
-					      GPI_NONE)>;
-			bias-pull-up;
-			drive-strength = <12>;
-			input-disable;
-			input-schmitt-disable;
-			slew-rate = <0>;
-		};
-
 		mmc-pins {
 			pinmux = <PINMUX(PAD_SD0_CLK, 0)>,
 				 <PINMUX(PAD_SD0_CMD, 0)>,
diff --git a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
index f2857d021d68..5a2a41a7e8c3 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
+++ b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
@@ -11,6 +11,55 @@ / {
 	compatible = "deepcomputing,fml13v01", "starfive,jh7110";
 };
 
+&cpu_opp {
+	opp-375000000 {
+		opp-hz = /bits/ 64 <375000000>;
+		opp-microvolt = <800000>;
+	};
+	opp-500000000 {
+		opp-hz = /bits/ 64 <500000000>;
+		opp-microvolt = <800000>;
+	};
+	opp-750000000 {
+		opp-hz = /bits/ 64 <750000000>;
+		opp-microvolt = <800000>;
+	};
+	opp-1500000000 {
+		opp-hz = /bits/ 64 <1500000000>;
+		opp-microvolt = <1040000>;
+	};
+};
+
+&mmc0 {
+	cap-mmc-highspeed;
+	cap-mmc-hw-reset;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&emmc_vdd>;
+};
+
+&mmc0_pins {
+	rst-pins {
+		pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
+				      GPOEN_ENABLE,
+				      GPI_NONE)>;
+		bias-pull-up;
+		drive-strength = <12>;
+		input-disable;
+		input-schmitt-disable;
+		slew-rate = <0>;
+	};
+};
+
+&mmc1 {
+	no-sdio;
+	no-mmc;
+	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	post-power-on-delay-ms = <200>;
+};
+
 &pcie1 {
 	perst-gpios = <&sysgpio 21 GPIO_ACTIVE_LOW>;
 	phys = <&pciephy1>;
diff --git a/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts b/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts
index fdaf6b4557da..96f6b2f072d4 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts
+++ b/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts
@@ -11,6 +11,25 @@ / {
 	compatible = "milkv,mars", "starfive,jh7110";
 };
 
+&cpu_opp {
+	opp-375000000 {
+		opp-hz = /bits/ 64 <375000000>;
+		opp-microvolt = <800000>;
+	};
+	opp-500000000 {
+		opp-hz = /bits/ 64 <500000000>;
+		opp-microvolt = <800000>;
+	};
+	opp-750000000 {
+		opp-hz = /bits/ 64 <750000000>;
+		opp-microvolt = <800000>;
+	};
+	opp-1500000000 {
+		opp-hz = /bits/ 64 <1500000000>;
+		opp-microvolt = <1040000>;
+	};
+};
+
 &gmac0 {
 	assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
 	assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
@@ -22,6 +41,36 @@ &i2c0 {
 	status = "okay";
 };
 
+&mmc0 {
+	cap-mmc-highspeed;
+	cap-mmc-hw-reset;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&emmc_vdd>;
+};
+
+&mmc0_pins {
+	rst-pins {
+		pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
+				      GPOEN_ENABLE,
+				      GPI_NONE)>;
+		bias-pull-up;
+		drive-strength = <12>;
+		input-disable;
+		input-schmitt-disable;
+		slew-rate = <0>;
+	};
+};
+
+&mmc1 {
+	no-sdio;
+	no-mmc;
+	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	post-power-on-delay-ms = <200>;
+};
+
 &pcie0 {
 	status = "okay";
 };
diff --git a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
index 31e825be2065..c9677aef9ff0 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
+++ b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
@@ -14,6 +14,25 @@ aliases {
 	};
 };
 
+&cpu_opp {
+	opp-375000000 {
+		opp-hz = /bits/ 64 <375000000>;
+		opp-microvolt = <800000>;
+	};
+	opp-500000000 {
+		opp-hz = /bits/ 64 <500000000>;
+		opp-microvolt = <800000>;
+	};
+	opp-750000000 {
+		opp-hz = /bits/ 64 <750000000>;
+		opp-microvolt = <800000>;
+	};
+	opp-1500000000 {
+		opp-hz = /bits/ 64 <1500000000>;
+		opp-microvolt = <1040000>;
+	};
+};
+
 &gmac0 {
 	starfive,tx-use-rgmii-clk;
 	assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
@@ -44,6 +63,36 @@ &i2c0 {
 	status = "okay";
 };
 
+&mmc0 {
+	cap-mmc-highspeed;
+	cap-mmc-hw-reset;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&emmc_vdd>;
+};
+
+&mmc0_pins {
+	rst-pins {
+		pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
+				      GPOEN_ENABLE,
+				      GPI_NONE)>;
+		bias-pull-up;
+		drive-strength = <12>;
+		input-disable;
+		input-schmitt-disable;
+		slew-rate = <0>;
+	};
+};
+
+&mmc1 {
+	no-sdio;
+	no-mmc;
+	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	post-power-on-delay-ms = <200>;
+};
+
 &pcie1 {
 	status = "okay";
 };
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index 5f14afb2c24d..d1e4206f1251 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -13,6 +13,25 @@ aliases {
 	};
 };
 
+&cpu_opp {
+	opp-375000000 {
+		opp-hz = /bits/ 64 <375000000>;
+		opp-microvolt = <800000>;
+	};
+	opp-500000000 {
+		opp-hz = /bits/ 64 <500000000>;
+		opp-microvolt = <800000>;
+	};
+	opp-750000000 {
+		opp-hz = /bits/ 64 <750000000>;
+		opp-microvolt = <800000>;
+	};
+	opp-1500000000 {
+		opp-hz = /bits/ 64 <1500000000>;
+		opp-microvolt = <1040000>;
+	};
+};
+
 &gmac0 {
 	status = "okay";
 };
@@ -38,9 +57,36 @@ &i2c0 {
 };
 
 &mmc0 {
+	cap-mmc-highspeed;
+	cap-mmc-hw-reset;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&emmc_vdd>;
 	non-removable;
 };
 
+&mmc0_pins {
+	rst-pins {
+		pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
+				      GPOEN_ENABLE,
+				      GPI_NONE)>;
+		bias-pull-up;
+		drive-strength = <12>;
+		input-disable;
+		input-schmitt-disable;
+		slew-rate = <0>;
+	};
+};
+
+&mmc1 {
+	no-sdio;
+	no-mmc;
+	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	post-power-on-delay-ms = <200>;
+};
+
 &pcie0 {
 	status = "okay";
 };
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 0ba74ef04679..d2463399b959 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -200,22 +200,6 @@ core4 {
 	cpu_opp: opp-table-0 {
 			compatible = "operating-points-v2";
 			opp-shared;
-			opp-375000000 {
-					opp-hz = /bits/ 64 <375000000>;
-					opp-microvolt = <800000>;
-			};
-			opp-500000000 {
-					opp-hz = /bits/ 64 <500000000>;
-					opp-microvolt = <800000>;
-			};
-			opp-750000000 {
-					opp-hz = /bits/ 64 <750000000>;
-					opp-microvolt = <800000>;
-			};
-			opp-1500000000 {
-					opp-hz = /bits/ 64 <1500000000>;
-					opp-microvolt = <1040000>;
-			};
 	};
 
 	thermal-zones {
-- 
2.43.2


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[RFC 3/3] riscv: dts: starfive: Add VisionFive 2 Lite board device tree

[Hal Feng]

VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S SoC.

Board features:
- JH7110S SoC
- 2/4/8 GiB LPDDR4 DRAM
- AXP15060 PMIC
- 40 pin GPIO header
- 1x USB 3.0 host port
- 3x USB 2.0 host port
- 1x M.2 M-Key (size: 2242)
- 1x MicroSD slot (optional non-removable eMMC)
- 1x QSPI Flash
- 1x I2C EEPROM
- 1x 1Gbps Ethernet port
- SDIO-based Wi-Fi & UART-based Bluetooth
- 1x HDMI port
- 1x 2-lane DSI
- 1x 2-lane CSI

Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
 arch/riscv/boot/dts/starfive/Makefile         |   2 +
 .../jh7110s-starfive-visionfive-2-lite.dts    | 152 ++++++++++++++++++
 2 files changed, 154 insertions(+)
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dts

diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
index b3bb12f78e7d..7265c363e2a9 100644
--- a/arch/riscv/boot/dts/starfive/Makefile
+++ b/arch/riscv/boot/dts/starfive/Makefile
@@ -13,3 +13,5 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-mars.dtb
 dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-pine64-star64.dtb
 dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
 dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
+
+dtb-$(CONFIG_ARCH_STARFIVE) += jh7110s-starfive-visionfive-2-lite.dtb
diff --git a/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dts b/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dts
new file mode 100644
index 000000000000..a0cb9912eb80
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dts
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2025 StarFive Technology Co., Ltd.
+ * Copyright (C) 2025 Hal Feng <hal.feng@starfivetech.com>
+ */
+
+/dts-v1/;
+#include "jh7110-common.dtsi"
+
+/ {
+	model = "StarFive VisionFive 2 Lite";
+	compatible = "starfive,visionfive-2-lite", "starfive,jh7110s";
+};
+
+&cpu_opp {
+	opp-312500000 {
+		opp-hz = /bits/ 64 <312500000>;
+		opp-microvolt = <800000>;
+	};
+	opp-417000000 {
+		opp-hz = /bits/ 64 <417000000>;
+		opp-microvolt = <800000>;
+	};
+	opp-625000000 {
+		opp-hz = /bits/ 64 <625000000>;
+		opp-microvolt = <800000>;
+	};
+	opp-1250000000 {
+		opp-hz = /bits/ 64 <1250000000>;
+		opp-microvolt = <1000000>;
+	};
+};
+
+&gmac0 {
+	starfive,tx-use-rgmii-clk;
+	assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
+	assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&mmc0 {
+	bus-width = <4>;
+	no-sdio;
+	no-mmc;
+	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_HIGH>;
+	disable-wp;
+	cap-sd-highspeed;
+};
+
+&mmc1 {
+	max-frequency = <50000000>;
+	keep-power-in-suspend;
+	non-removable;
+};
+
+&pcie1 {
+	enable-gpios = <&sysgpio 27 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&phy0 {
+	motorcomm,tx-clk-adj-enabled;
+	motorcomm,tx-clk-100-inverted;
+	motorcomm,tx-clk-1000-inverted;
+	motorcomm,rx-clk-drv-microamp = <3970>;
+	motorcomm,rx-data-drv-microamp = <2910>;
+	rx-internal-delay-ps = <1500>;
+	tx-internal-delay-ps = <1500>;
+};
+
+&pwm {
+	status = "okay";
+};
+
+&spi0 {
+	status = "okay";
+};
+
+&syscrg {
+	assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>, <1250000000>;
+};
+
+&sysgpio {
+	uart1_pins: uart1-0 {
+		tx-pins {
+			pinmux = <GPIOMUX(22, GPOUT_SYS_UART1_TX,
+					      GPOEN_ENABLE,
+					      GPI_NONE)>;
+			bias-disable;
+			drive-strength = <12>;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+
+		rx-pins {
+			pinmux = <GPIOMUX(23, GPOUT_LOW,
+					      GPOEN_DISABLE,
+					      GPI_SYS_UART1_RX)>;
+			bias-pull-up;
+			drive-strength = <2>;
+			input-enable;
+			input-schmitt-enable;
+			slew-rate = <0>;
+		};
+
+		cts-pins {
+			pinmux = <GPIOMUX(24, GPOUT_LOW,
+					      GPOEN_DISABLE,
+					      GPI_SYS_UART1_CTS)>;
+			input-enable;
+		};
+
+		rts-pins {
+			pinmux = <GPIOMUX(25, GPOUT_SYS_UART1_RTS,
+					      GPOEN_ENABLE,
+					      GPI_NONE)>;
+			input-enable;
+		};
+	};
+
+	usb0_pins: usb0-0 {
+		power-pins {
+			pinmux = <GPIOMUX(26, GPOUT_HIGH,
+					      GPOEN_ENABLE,
+					      GPI_NONE)>;
+			input-disable;
+		};
+	};
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins>;
+	status = "okay";
+};
+
+&usb0 {
+	dr_mode = "host";
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb0_pins>;
+	status = "okay";
+};
+
+&usb_cdns3 {
+	phys = <&usbphy0>, <&pciephy0>;
+	phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy";
+};
-- 
2.43.2


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Re: [RFC 3/3] riscv: dts: starfive: Add VisionFive 2 Lite board device tree

[Vivian Wang]

On 8/21/25 18:09, Hal Feng wrote:
> [...]
> +++ b/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dts
> @@ -0,0 +1,152 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2025 StarFive Technology Co., Ltd.
> + * Copyright (C) 2025 Hal Feng <hal.feng@starfivetech.com>
> + */
> +
> +/dts-v1/;
> +#include "jh7110-common.dtsi"
> +
> +/ {
> +	model = "StarFive VisionFive 2 Lite";
> +	compatible = "starfive,visionfive-2-lite", "starfive,jh7110s";
> +};

Might need to add starfive,jh7110s to:

  drivers/cpufreq/cpufreq-dt-platdev.c

So that it can use the opp stuff here:

> +
> +&cpu_opp {
> +	opp-312500000 {
> +		opp-hz = /bits/ 64 <312500000>;
> +		opp-microvolt = <800000>;
> +	};
> +	opp-417000000 {
> +		opp-hz = /bits/ 64 <417000000>;
> +		opp-microvolt = <800000>;
> +	};
> +	opp-625000000 {
> +		opp-hz = /bits/ 64 <625000000>;
> +		opp-microvolt = <800000>;
> +	};
> +	opp-1250000000 {
> +		opp-hz = /bits/ 64 <1250000000>;
> +		opp-microvolt = <1000000>;
> +	};
> +};
> +> [...]


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Re: [RFC 2/3] riscv: dts: starfive: jh7110-common: Move out some nodes to the board dts

[E Shattow]

On 8/21/25 03:09, Hal Feng wrote:
> Some node in this file are not used by the upcoming VisionFive 2 Lite
> board. Move them to the board dts to prepare for adding the new
> VisionFive 2 Lite device tree.
> 
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
>  .../boot/dts/starfive/jh7110-common.dtsi      | 22 ---------
>  .../jh7110-deepcomputing-fml13v01.dts         | 49 +++++++++++++++++++
>  .../boot/dts/starfive/jh7110-milkv-mars.dts   | 49 +++++++++++++++++++
>  .../dts/starfive/jh7110-pine64-star64.dts     | 49 +++++++++++++++++++
>  .../jh7110-starfive-visionfive-2.dtsi         | 46 +++++++++++++++++
>  arch/riscv/boot/dts/starfive/jh7110.dtsi      | 16 ------
>  6 files changed, 193 insertions(+), 38 deletions(-)
> 
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> index 2eaf01775ef5..8332622420ca 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> @@ -281,15 +281,9 @@ &mmc0 {
>  	assigned-clock-rates = <50000000>;
>  	bus-width = <8>;
>  	bootph-pre-ram;
> -	cap-mmc-highspeed;
> -	mmc-ddr-1_8v;
> -	mmc-hs200-1_8v;
> -	cap-mmc-hw-reset;
>  	post-power-on-delay-ms = <200>;
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&mmc0_pins>;
> -	vmmc-supply = <&vcc_3v3>;
> -	vqmmc-supply = <&emmc_vdd>;
>  	status = "okay";
>  };
>  
> @@ -299,12 +293,7 @@ &mmc1 {
>  	assigned-clock-rates = <50000000>;
>  	bus-width = <4>;
>  	bootph-pre-ram;

> -	no-sdio;

drop no-sdio, it is not there in riscv-dt-for-next branch
ref: https://lore.kernel.org/lkml/20250819-sushi-change-1254c2d2a08d@spud/

> -	no-mmc;

similar, I think we should now drop no-mmc unless you can say there is a
defect which requires it. I have tested with Star64 and Milk-V Mars
CM(/-Lite);  if you can confirm with boards you have access to that
'no-mmc' can be dropped then we should just drop it. The correct reason
for having this 'no-mmc' would only be if the controller has an error
when receiving these commands.

> -	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
> -	disable-wp;
>  	cap-sd-highspeed;

> -	post-power-on-delay-ms = <200>;

I would like to know the reason for this delay configuration? Is it
described somewhere in technical documentation or discussion why we have
this?

>  	pinctrl-names = "default";
>  	pinctrl-0 = <&mmc1_pins>;
>  	status = "okay";
> @@ -448,17 +437,6 @@ GPOEN_SYS_I2C6_DATA,
>  	};
>  
>  	mmc0_pins: mmc0-0 {
> -		 rst-pins {
> -			pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
> -					      GPOEN_ENABLE,
> -					      GPI_NONE)>;
> -			bias-pull-up;
> -			drive-strength = <12>;
> -			input-disable;
> -			input-schmitt-disable;
> -			slew-rate = <0>;
> -		};
> -
>  		mmc-pins {
>  			pinmux = <PINMUX(PAD_SD0_CLK, 0)>,
>  				 <PINMUX(PAD_SD0_CMD, 0)>,
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
> index f2857d021d68..5a2a41a7e8c3 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
> +++ b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
> @@ -11,6 +11,55 @@ / {
>  	compatible = "deepcomputing,fml13v01", "starfive,jh7110";
>  };
>  
> +&cpu_opp {
> +	opp-375000000 {
> +		opp-hz = /bits/ 64 <375000000>;
> +		opp-microvolt = <800000>;
> +	};
> +	opp-500000000 {
> +		opp-hz = /bits/ 64 <500000000>;
> +		opp-microvolt = <800000>;
> +	};
> +	opp-750000000 {
> +		opp-hz = /bits/ 64 <750000000>;
> +		opp-microvolt = <800000>;
> +	};
> +	opp-1500000000 {
> +		opp-hz = /bits/ 64 <1500000000>;
> +		opp-microvolt = <1040000>;
> +	};
> +};
> +
> +&mmc0 {
> +	cap-mmc-highspeed;
> +	cap-mmc-hw-reset;
> +	mmc-ddr-1_8v;
> +	mmc-hs200-1_8v;
> +	vmmc-supply = <&vcc_3v3>;
> +	vqmmc-supply = <&emmc_vdd>;
> +};
> +
> +&mmc0_pins {
> +	rst-pins {
> +		pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
> +				      GPOEN_ENABLE,
> +				      GPI_NONE)>;
> +		bias-pull-up;
> +		drive-strength = <12>;
> +		input-disable;
> +		input-schmitt-disable;
> +		slew-rate = <0>;
> +	};
> +};
> +
> +&mmc1 {
> +	no-sdio;
> +	no-mmc;
> +	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
> +	disable-wp;
> +	post-power-on-delay-ms = <200>;
> +};
> +
>  &pcie1 {
>  	perst-gpios = <&sysgpio 21 GPIO_ACTIVE_LOW>;
>  	phys = <&pciephy1>;
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts b/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts
> index fdaf6b4557da..96f6b2f072d4 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts
> +++ b/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts
> @@ -11,6 +11,25 @@ / {
>  	compatible = "milkv,mars", "starfive,jh7110";
>  };
>  
> +&cpu_opp {
> +	opp-375000000 {
> +		opp-hz = /bits/ 64 <375000000>;
> +		opp-microvolt = <800000>;
> +	};
> +	opp-500000000 {
> +		opp-hz = /bits/ 64 <500000000>;
> +		opp-microvolt = <800000>;
> +	};
> +	opp-750000000 {
> +		opp-hz = /bits/ 64 <750000000>;
> +		opp-microvolt = <800000>;
> +	};
> +	opp-1500000000 {
> +		opp-hz = /bits/ 64 <1500000000>;
> +		opp-microvolt = <1040000>;
> +	};
> +};
> +
>  &gmac0 {
>  	assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
>  	assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
> @@ -22,6 +41,36 @@ &i2c0 {
>  	status = "okay";
>  };
>  
> +&mmc0 {
> +	cap-mmc-highspeed;
> +	cap-mmc-hw-reset;
> +	mmc-ddr-1_8v;
> +	mmc-hs200-1_8v;
> +	vmmc-supply = <&vcc_3v3>;
> +	vqmmc-supply = <&emmc_vdd>;
> +};
> +
> +&mmc0_pins {
> +	rst-pins {
> +		pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
> +				      GPOEN_ENABLE,
> +				      GPI_NONE)>;
> +		bias-pull-up;
> +		drive-strength = <12>;
> +		input-disable;
> +		input-schmitt-disable;
> +		slew-rate = <0>;
> +	};
> +};
> +
> +&mmc1 {
> +	no-sdio;
> +	no-mmc;
> +	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
> +	disable-wp;
> +	post-power-on-delay-ms = <200>;
> +};
> +
>  &pcie0 {
>  	status = "okay";
>  };
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
> index 31e825be2065..c9677aef9ff0 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
> +++ b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
> @@ -14,6 +14,25 @@ aliases {
>  	};
>  };
>  
> +&cpu_opp {
> +	opp-375000000 {
> +		opp-hz = /bits/ 64 <375000000>;
> +		opp-microvolt = <800000>;
> +	};
> +	opp-500000000 {
> +		opp-hz = /bits/ 64 <500000000>;
> +		opp-microvolt = <800000>;
> +	};
> +	opp-750000000 {
> +		opp-hz = /bits/ 64 <750000000>;
> +		opp-microvolt = <800000>;
> +	};
> +	opp-1500000000 {
> +		opp-hz = /bits/ 64 <1500000000>;
> +		opp-microvolt = <1040000>;
> +	};
> +};
> +
>  &gmac0 {
>  	starfive,tx-use-rgmii-clk;
>  	assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
> @@ -44,6 +63,36 @@ &i2c0 {
>  	status = "okay";
>  };
>  
> +&mmc0 {
> +	cap-mmc-highspeed;
> +	cap-mmc-hw-reset;
> +	mmc-ddr-1_8v;
> +	mmc-hs200-1_8v;
> +	vmmc-supply = <&vcc_3v3>;
> +	vqmmc-supply = <&emmc_vdd>;
> +};
> +
> +&mmc0_pins {
> +	rst-pins {
> +		pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
> +				      GPOEN_ENABLE,
> +				      GPI_NONE)>;
> +		bias-pull-up;
> +		drive-strength = <12>;
> +		input-disable;
> +		input-schmitt-disable;
> +		slew-rate = <0>;
> +	};
> +};
> +
> +&mmc1 {
> +	no-sdio;
> +	no-mmc;
> +	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
> +	disable-wp;
> +	post-power-on-delay-ms = <200>;
> +};
> +
>  &pcie1 {
>  	status = "okay";
>  };
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> index 5f14afb2c24d..d1e4206f1251 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> @@ -13,6 +13,25 @@ aliases {
>  	};
>  };
>  
> +&cpu_opp {
> +	opp-375000000 {
> +		opp-hz = /bits/ 64 <375000000>;
> +		opp-microvolt = <800000>;
> +	};
> +	opp-500000000 {
> +		opp-hz = /bits/ 64 <500000000>;
> +		opp-microvolt = <800000>;
> +	};
> +	opp-750000000 {
> +		opp-hz = /bits/ 64 <750000000>;
> +		opp-microvolt = <800000>;
> +	};
> +	opp-1500000000 {
> +		opp-hz = /bits/ 64 <1500000000>;
> +		opp-microvolt = <1040000>;
> +	};
> +};
> +
>  &gmac0 {
>  	status = "okay";
>  };
> @@ -38,9 +57,36 @@ &i2c0 {
>  };
>  
>  &mmc0 {
> +	cap-mmc-highspeed;
> +	cap-mmc-hw-reset;
> +	mmc-ddr-1_8v;
> +	mmc-hs200-1_8v;
> +	vmmc-supply = <&vcc_3v3>;
> +	vqmmc-supply = <&emmc_vdd>;
>  	non-removable;
>  };
>  
> +&mmc0_pins {
> +	rst-pins {
> +		pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
> +				      GPOEN_ENABLE,
> +				      GPI_NONE)>;
> +		bias-pull-up;
> +		drive-strength = <12>;
> +		input-disable;
> +		input-schmitt-disable;
> +		slew-rate = <0>;
> +	};
> +};
> +
> +&mmc1 {
> +	no-sdio;
> +	no-mmc;
> +	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
> +	disable-wp;
> +	post-power-on-delay-ms = <200>;
> +};
> +
>  &pcie0 {
>  	status = "okay";
>  };
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index 0ba74ef04679..d2463399b959 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -200,22 +200,6 @@ core4 {
>  	cpu_opp: opp-table-0 {
>  			compatible = "operating-points-v2";
>  			opp-shared;
> -			opp-375000000 {
> -					opp-hz = /bits/ 64 <375000000>;
> -					opp-microvolt = <800000>;
> -			};
> -			opp-500000000 {
> -					opp-hz = /bits/ 64 <500000000>;
> -					opp-microvolt = <800000>;
> -			};
> -			opp-750000000 {
> -					opp-hz = /bits/ 64 <750000000>;
> -					opp-microvolt = <800000>;
> -			};
> -			opp-1500000000 {
> -					opp-hz = /bits/ 64 <1500000000>;
> -					opp-microvolt = <1040000>;
> -			};
>  	};
>  
>  	thermal-zones {

With that,

Reviewed-by: E Shattow <e@freeshell.de>

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Re: [RFC 1/3] dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2 Lite board

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 1224 bytes --]

On Thu, Aug 21, 2025 at 06:09:28PM +0800, Hal Feng wrote:
> Add device tree bindings for the StarFive JH7110S SoC
> and the VisionFive 2 Lite board equipped with it.
> 
> JH7110S SoC is an industrial SoC which can run at -40~85 degrees centigrade
> and up to 1.25GHz. Its CPU cores and peripherals are mostly similar to
> those of the JH7110 SoC.

How "mostly" is mostly? Are there memory map or capability differences?

> 
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
>  Documentation/devicetree/bindings/riscv/starfive.yaml | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml
> index 7ef85174353d..a2952490709f 100644
> --- a/Documentation/devicetree/bindings/riscv/starfive.yaml
> +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
> @@ -33,6 +33,11 @@ properties:
>                - starfive,visionfive-2-v1.3b
>            - const: starfive,jh7110
>  
> +      - items:
> +          - enum:
> +              - starfive,visionfive-2-lite
> +          - const: starfive,jh7110s
> +
>  additionalProperties: true
>  
>  ...
> -- 
> 2.43.2
> 

[-- Attachment #1.2: signature.asc --]
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[-- Attachment #2: Type: text/plain, Size: 161 bytes --]

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RE: [RFC 3/3] riscv: dts: starfive: Add VisionFive 2 Lite board device tree

[Hal Feng]

> On 21.08.25 22:08, Vivian Wang wrote:
> On 8/21/25 18:09, Hal Feng wrote:
> > [...]
> > +++ b/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.
> > +++ dts
> > @@ -0,0 +1,152 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > +/*
> > + * Copyright (C) 2025 StarFive Technology Co., Ltd.
> > + * Copyright (C) 2025 Hal Feng <hal.feng@starfivetech.com>  */
> > +
> > +/dts-v1/;
> > +#include "jh7110-common.dtsi"
> > +
> > +/ {
> > +	model = "StarFive VisionFive 2 Lite";
> > +	compatible = "starfive,visionfive-2-lite", "starfive,jh7110s"; };
> 
> Might need to add starfive,jh7110s to:
> 
>   drivers/cpufreq/cpufreq-dt-platdev.c
> 
> So that it can use the opp stuff here:

Good catch. Thanks for your review.

Best regards,
Hal

> 
> > +
> > +&cpu_opp {
> > +	opp-312500000 {
> > +		opp-hz = /bits/ 64 <312500000>;
> > +		opp-microvolt = <800000>;
> > +	};
> > +	opp-417000000 {
> > +		opp-hz = /bits/ 64 <417000000>;
> > +		opp-microvolt = <800000>;
> > +	};
> > +	opp-625000000 {
> > +		opp-hz = /bits/ 64 <625000000>;
> > +		opp-microvolt = <800000>;
> > +	};
> > +	opp-1250000000 {
> > +		opp-hz = /bits/ 64 <1250000000>;
> > +		opp-microvolt = <1000000>;
> > +	};
> > +};
> > +> [...]

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RE: [RFC 2/3] riscv: dts: starfive: jh7110-common: Move out some nodes to the board dts

[Hal Feng]

> On 21.08.25 23:08, E Shattow wrote:
> On 8/21/25 03:09, Hal Feng wrote:
> > Some node in this file are not used by the upcoming VisionFive 2 Lite
> > board. Move them to the board dts to prepare for adding the new
> > VisionFive 2 Lite device tree.
> >
> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> > ---
> >  .../boot/dts/starfive/jh7110-common.dtsi      | 22 ---------
> >  .../jh7110-deepcomputing-fml13v01.dts         | 49 +++++++++++++++++++
> >  .../boot/dts/starfive/jh7110-milkv-mars.dts   | 49 +++++++++++++++++++
> >  .../dts/starfive/jh7110-pine64-star64.dts     | 49 +++++++++++++++++++
> >  .../jh7110-starfive-visionfive-2.dtsi         | 46 +++++++++++++++++
> >  arch/riscv/boot/dts/starfive/jh7110.dtsi      | 16 ------
> >  6 files changed, 193 insertions(+), 38 deletions(-)
> >
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> > b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> > index 2eaf01775ef5..8332622420ca 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> > +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> > @@ -281,15 +281,9 @@ &mmc0 {
> >  	assigned-clock-rates = <50000000>;
> >  	bus-width = <8>;
> >  	bootph-pre-ram;
> > -	cap-mmc-highspeed;
> > -	mmc-ddr-1_8v;
> > -	mmc-hs200-1_8v;
> > -	cap-mmc-hw-reset;
> >  	post-power-on-delay-ms = <200>;
> >  	pinctrl-names = "default";
> >  	pinctrl-0 = <&mmc0_pins>;
> > -	vmmc-supply = <&vcc_3v3>;
> > -	vqmmc-supply = <&emmc_vdd>;
> >  	status = "okay";
> >  };
> >
> > @@ -299,12 +293,7 @@ &mmc1 {
> >  	assigned-clock-rates = <50000000>;
> >  	bus-width = <4>;
> >  	bootph-pre-ram;
> 
> > -	no-sdio;
> 
> drop no-sdio, it is not there in riscv-dt-for-next branch
> ref: https://lore.kernel.org/lkml/20250819-sushi-change-
> 1254c2d2a08d@spud/

OK. Thanks for pointing it out.

> 
> > -	no-mmc;
> 
> similar, I think we should now drop no-mmc unless you can say there is a
> defect which requires it. I have tested with Star64 and Milk-V Mars CM(/-Lite);
> if you can confirm with boards you have access to that 'no-mmc' can be
> dropped then we should just drop it. The correct reason for having this 'no-
> mmc' would only be if the controller has an error when receiving these
> commands.

I tested successfully on VF2 v1.3b and VF2 Lite without "no-sdio", "no-mmc" and
"post-power-on-delay-ms". So let's drop them. 

> 
> > -	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
> > -	disable-wp;
> >  	cap-sd-highspeed;
> 
> > -	post-power-on-delay-ms = <200>;
> 
> I would like to know the reason for this delay configuration? Is it described
> somewhere in technical documentation or discussion why we have this?

The source of this property can not be found now. Let's drop it.

> 
> >  	pinctrl-names = "default";
> >  	pinctrl-0 = <&mmc1_pins>;
> >  	status = "okay";
> > @@ -448,17 +437,6 @@ GPOEN_SYS_I2C6_DATA,
> >  	};
> >
> >  	mmc0_pins: mmc0-0 {
> > -		 rst-pins {
> > -			pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
> > -					      GPOEN_ENABLE,
> > -					      GPI_NONE)>;
> > -			bias-pull-up;
> > -			drive-strength = <12>;
> > -			input-disable;
> > -			input-schmitt-disable;
> > -			slew-rate = <0>;
> > -		};
> > -
> >  		mmc-pins {
> >  			pinmux = <PINMUX(PAD_SD0_CLK, 0)>,
> >  				 <PINMUX(PAD_SD0_CMD, 0)>,
> > diff --git
> > a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
> > b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
> > index f2857d021d68..5a2a41a7e8c3 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
> > +++ b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
> > @@ -11,6 +11,55 @@ / {
> >  	compatible = "deepcomputing,fml13v01", "starfive,jh7110";  };
> >
> > +&cpu_opp {
> > +	opp-375000000 {
> > +		opp-hz = /bits/ 64 <375000000>;
> > +		opp-microvolt = <800000>;
> > +	};
> > +	opp-500000000 {
> > +		opp-hz = /bits/ 64 <500000000>;
> > +		opp-microvolt = <800000>;
> > +	};
> > +	opp-750000000 {
> > +		opp-hz = /bits/ 64 <750000000>;
> > +		opp-microvolt = <800000>;
> > +	};
> > +	opp-1500000000 {
> > +		opp-hz = /bits/ 64 <1500000000>;
> > +		opp-microvolt = <1040000>;
> > +	};
> > +};
> > +
> > +&mmc0 {
> > +	cap-mmc-highspeed;
> > +	cap-mmc-hw-reset;
> > +	mmc-ddr-1_8v;
> > +	mmc-hs200-1_8v;
> > +	vmmc-supply = <&vcc_3v3>;
> > +	vqmmc-supply = <&emmc_vdd>;
> > +};
> > +
> > +&mmc0_pins {
> > +	rst-pins {
> > +		pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
> > +				      GPOEN_ENABLE,
> > +				      GPI_NONE)>;
> > +		bias-pull-up;
> > +		drive-strength = <12>;
> > +		input-disable;
> > +		input-schmitt-disable;
> > +		slew-rate = <0>;
> > +	};
> > +};
> > +
> > +&mmc1 {
> > +	no-sdio;
> > +	no-mmc;
> > +	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
> > +	disable-wp;
> > +	post-power-on-delay-ms = <200>;
> > +};
> > +
> >  &pcie1 {
> >  	perst-gpios = <&sysgpio 21 GPIO_ACTIVE_LOW>;
> >  	phys = <&pciephy1>;
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts
> > b/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts
> > index fdaf6b4557da..96f6b2f072d4 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts
> > +++ b/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts
> > @@ -11,6 +11,25 @@ / {
> >  	compatible = "milkv,mars", "starfive,jh7110";  };
> >
> > +&cpu_opp {
> > +	opp-375000000 {
> > +		opp-hz = /bits/ 64 <375000000>;
> > +		opp-microvolt = <800000>;
> > +	};
> > +	opp-500000000 {
> > +		opp-hz = /bits/ 64 <500000000>;
> > +		opp-microvolt = <800000>;
> > +	};
> > +	opp-750000000 {
> > +		opp-hz = /bits/ 64 <750000000>;
> > +		opp-microvolt = <800000>;
> > +	};
> > +	opp-1500000000 {
> > +		opp-hz = /bits/ 64 <1500000000>;
> > +		opp-microvolt = <1040000>;
> > +	};
> > +};
> > +
> >  &gmac0 {
> >  	assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
> >  	assigned-clock-parents = <&aoncrg
> JH7110_AONCLK_GMAC0_RMII_RTX>; @@
> > -22,6 +41,36 @@ &i2c0 {
> >  	status = "okay";
> >  };
> >
> > +&mmc0 {
> > +	cap-mmc-highspeed;
> > +	cap-mmc-hw-reset;
> > +	mmc-ddr-1_8v;
> > +	mmc-hs200-1_8v;
> > +	vmmc-supply = <&vcc_3v3>;
> > +	vqmmc-supply = <&emmc_vdd>;
> > +};
> > +
> > +&mmc0_pins {
> > +	rst-pins {
> > +		pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
> > +				      GPOEN_ENABLE,
> > +				      GPI_NONE)>;
> > +		bias-pull-up;
> > +		drive-strength = <12>;
> > +		input-disable;
> > +		input-schmitt-disable;
> > +		slew-rate = <0>;
> > +	};
> > +};
> > +
> > +&mmc1 {
> > +	no-sdio;
> > +	no-mmc;
> > +	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
> > +	disable-wp;
> > +	post-power-on-delay-ms = <200>;
> > +};
> > +
> >  &pcie0 {
> >  	status = "okay";
> >  };
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
> > b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
> > index 31e825be2065..c9677aef9ff0 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
> > +++ b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
> > @@ -14,6 +14,25 @@ aliases {
> >  	};
> >  };
> >
> > +&cpu_opp {
> > +	opp-375000000 {
> > +		opp-hz = /bits/ 64 <375000000>;
> > +		opp-microvolt = <800000>;
> > +	};
> > +	opp-500000000 {
> > +		opp-hz = /bits/ 64 <500000000>;
> > +		opp-microvolt = <800000>;
> > +	};
> > +	opp-750000000 {
> > +		opp-hz = /bits/ 64 <750000000>;
> > +		opp-microvolt = <800000>;
> > +	};
> > +	opp-1500000000 {
> > +		opp-hz = /bits/ 64 <1500000000>;
> > +		opp-microvolt = <1040000>;
> > +	};
> > +};
> > +
> >  &gmac0 {
> >  	starfive,tx-use-rgmii-clk;
> >  	assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>; @@ -
> 44,6 +63,36
> > @@ &i2c0 {
> >  	status = "okay";
> >  };
> >
> > +&mmc0 {
> > +	cap-mmc-highspeed;
> > +	cap-mmc-hw-reset;
> > +	mmc-ddr-1_8v;
> > +	mmc-hs200-1_8v;
> > +	vmmc-supply = <&vcc_3v3>;
> > +	vqmmc-supply = <&emmc_vdd>;
> > +};
> > +
> > +&mmc0_pins {
> > +	rst-pins {
> > +		pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
> > +				      GPOEN_ENABLE,
> > +				      GPI_NONE)>;
> > +		bias-pull-up;
> > +		drive-strength = <12>;
> > +		input-disable;
> > +		input-schmitt-disable;
> > +		slew-rate = <0>;
> > +	};
> > +};
> > +
> > +&mmc1 {
> > +	no-sdio;
> > +	no-mmc;
> > +	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
> > +	disable-wp;
> > +	post-power-on-delay-ms = <200>;
> > +};
> > +
> >  &pcie1 {
> >  	status = "okay";
> >  };
> > diff --git
> > a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> > b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> > index 5f14afb2c24d..d1e4206f1251 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> > @@ -13,6 +13,25 @@ aliases {
> >  	};
> >  };
> >
> > +&cpu_opp {
> > +	opp-375000000 {
> > +		opp-hz = /bits/ 64 <375000000>;
> > +		opp-microvolt = <800000>;
> > +	};
> > +	opp-500000000 {
> > +		opp-hz = /bits/ 64 <500000000>;
> > +		opp-microvolt = <800000>;
> > +	};
> > +	opp-750000000 {
> > +		opp-hz = /bits/ 64 <750000000>;
> > +		opp-microvolt = <800000>;
> > +	};
> > +	opp-1500000000 {
> > +		opp-hz = /bits/ 64 <1500000000>;
> > +		opp-microvolt = <1040000>;
> > +	};
> > +};
> > +
> >  &gmac0 {
> >  	status = "okay";
> >  };
> > @@ -38,9 +57,36 @@ &i2c0 {
> >  };
> >
> >  &mmc0 {
> > +	cap-mmc-highspeed;
> > +	cap-mmc-hw-reset;
> > +	mmc-ddr-1_8v;
> > +	mmc-hs200-1_8v;
> > +	vmmc-supply = <&vcc_3v3>;
> > +	vqmmc-supply = <&emmc_vdd>;
> >  	non-removable;
> >  };
> >
> > +&mmc0_pins {
> > +	rst-pins {
> > +		pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
> > +				      GPOEN_ENABLE,
> > +				      GPI_NONE)>;
> > +		bias-pull-up;
> > +		drive-strength = <12>;
> > +		input-disable;
> > +		input-schmitt-disable;
> > +		slew-rate = <0>;
> > +	};
> > +};
> > +
> > +&mmc1 {
> > +	no-sdio;
> > +	no-mmc;
> > +	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
> > +	disable-wp;
> > +	post-power-on-delay-ms = <200>;
> > +};
> > +
> >  &pcie0 {
> >  	status = "okay";
> >  };
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > index 0ba74ef04679..d2463399b959 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > @@ -200,22 +200,6 @@ core4 {
> >  	cpu_opp: opp-table-0 {
> >  			compatible = "operating-points-v2";
> >  			opp-shared;
> > -			opp-375000000 {
> > -					opp-hz = /bits/ 64 <375000000>;
> > -					opp-microvolt = <800000>;
> > -			};
> > -			opp-500000000 {
> > -					opp-hz = /bits/ 64 <500000000>;
> > -					opp-microvolt = <800000>;
> > -			};
> > -			opp-750000000 {
> > -					opp-hz = /bits/ 64 <750000000>;
> > -					opp-microvolt = <800000>;
> > -			};
> > -			opp-1500000000 {
> > -					opp-hz = /bits/ 64 <1500000000>;
> > -					opp-microvolt = <1040000>;
> > -			};
> >  	};
> >
> >  	thermal-zones {
> 
> With that,
> 
> Reviewed-by: E Shattow <e@freeshell.de>

Thanks for your review.

Best regards,
Hal
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RE: [RFC 1/3] dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2 Lite board

[Hal Feng]

> On 22.08.25 02:17, Conor Dooley wrote:
> On Thu, Aug 21, 2025 at 06:09:28PM +0800, Hal Feng wrote:
> > Add device tree bindings for the StarFive JH7110S SoC and the
> > VisionFive 2 Lite board equipped with it.
> >
> > JH7110S SoC is an industrial SoC which can run at -40~85 degrees
> > centigrade and up to 1.25GHz. Its CPU cores and peripherals are mostly
> > similar to those of the JH7110 SoC.
> 
> How "mostly" is mostly? Are there memory map or capability differences?

To be precise, the CPU cores and peripherals are the same as those of the
JH7110 SoC. I will improve the commit description in the next version.

Here are the differences between them: 
JH7110 supports 0~70 degrees centigrade and up to 1.5GHz.
JH7110S supports -40~85 degrees centigrade and up to 1.25GHz.

Best regards,
Hal

> 
> >
> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> > ---
> >  Documentation/devicetree/bindings/riscv/starfive.yaml | 5 +++++
> >  1 file changed, 5 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml
> > b/Documentation/devicetree/bindings/riscv/starfive.yaml
> > index 7ef85174353d..a2952490709f 100644
> > --- a/Documentation/devicetree/bindings/riscv/starfive.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
> > @@ -33,6 +33,11 @@ properties:
> >                - starfive,visionfive-2-v1.3b
> >            - const: starfive,jh7110
> >
> > +      - items:
> > +          - enum:
> > +              - starfive,visionfive-2-lite
> > +          - const: starfive,jh7110s
> > +
> >  additionalProperties: true
> >
> >  ...
> > --
> > 2.43.2
> >

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Re: [RFC 1/3] dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2 Lite board

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 2006 bytes --]

On Fri, Aug 22, 2025 at 07:37:29AM +0000, Hal Feng wrote:
> > On 22.08.25 02:17, Conor Dooley wrote:
> > On Thu, Aug 21, 2025 at 06:09:28PM +0800, Hal Feng wrote:
> > > Add device tree bindings for the StarFive JH7110S SoC and the
> > > VisionFive 2 Lite board equipped with it.
> > >
> > > JH7110S SoC is an industrial SoC which can run at -40~85 degrees
> > > centigrade and up to 1.25GHz. Its CPU cores and peripherals are mostly
> > > similar to those of the JH7110 SoC.
> > 
> > How "mostly" is mostly? Are there memory map or capability differences?
> 
> To be precise, the CPU cores and peripherals are the same as those of the
> JH7110 SoC. I will improve the commit description in the next version.

Ye, please do. The complete lack of differences other than thermals
and cpu performance is what allows you to use all the same compatibles
for the peripherals after all!

> 
> Here are the differences between them: 
> JH7110 supports 0~70 degrees centigrade and up to 1.5GHz.
> JH7110S supports -40~85 degrees centigrade and up to 1.25GHz.
> 
> Best regards,
> Hal
> 
> > 
> > >
> > > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> > > ---
> > >  Documentation/devicetree/bindings/riscv/starfive.yaml | 5 +++++
> > >  1 file changed, 5 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml
> > > b/Documentation/devicetree/bindings/riscv/starfive.yaml
> > > index 7ef85174353d..a2952490709f 100644
> > > --- a/Documentation/devicetree/bindings/riscv/starfive.yaml
> > > +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
> > > @@ -33,6 +33,11 @@ properties:
> > >                - starfive,visionfive-2-v1.3b
> > >            - const: starfive,jh7110
> > >
> > > +      - items:
> > > +          - enum:
> > > +              - starfive,visionfive-2-lite
> > > +          - const: starfive,jh7110s
> > > +
> > >  additionalProperties: true
> > >
> > >  ...
> > > --
> > > 2.43.2
> > >
> 

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Re: [RFC 3/3] riscv: dts: starfive: Add VisionFive 2 Lite board device tree

[E Shattow]

On 8/21/25 03:09, Hal Feng wrote:
> VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S SoC.
> 
> Board features:
> - JH7110S SoC
> - 2/4/8 GiB LPDDR4 DRAM
> - AXP15060 PMIC
> - 40 pin GPIO header
> - 1x USB 3.0 host port
> - 3x USB 2.0 host port
> - 1x M.2 M-Key (size: 2242)
> - 1x MicroSD slot (optional non-removable eMMC)
> - 1x QSPI Flash
> - 1x I2C EEPROM
> - 1x 1Gbps Ethernet port
> - SDIO-based Wi-Fi & UART-based Bluetooth
> - 1x HDMI port
> - 1x 2-lane DSI
> - 1x 2-lane CSI
> 
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
>  arch/riscv/boot/dts/starfive/Makefile         |   2 +
>  .../jh7110s-starfive-visionfive-2-lite.dts    | 152 ++++++++++++++++++
>  2 files changed, 154 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dts
> 
> diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
> index b3bb12f78e7d..7265c363e2a9 100644
> --- a/arch/riscv/boot/dts/starfive/Makefile
> +++ b/arch/riscv/boot/dts/starfive/Makefile
> @@ -13,3 +13,5 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-mars.dtb
>  dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-pine64-star64.dtb
>  dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
>  dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
> +
> +dtb-$(CONFIG_ARCH_STARFIVE) += jh7110s-starfive-visionfive-2-lite.dtb
> diff --git a/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dts b/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dts
> new file mode 100644
> index 000000000000..a0cb9912eb80
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dts
> @@ -0,0 +1,152 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2025 StarFive Technology Co., Ltd.
> + * Copyright (C) 2025 Hal Feng <hal.feng@starfivetech.com>
> + */
> +
> +/dts-v1/;
> +#include "jh7110-common.dtsi"
> +
> +/ {
> +	model = "StarFive VisionFive 2 Lite";
> +	compatible = "starfive,visionfive-2-lite", "starfive,jh7110s";
> +};
> +
> +&cpu_opp {
> +	opp-312500000 {
> +		opp-hz = /bits/ 64 <312500000>;
> +		opp-microvolt = <800000>;
> +	};
> +	opp-417000000 {
> +		opp-hz = /bits/ 64 <417000000>;
> +		opp-microvolt = <800000>;
> +	};
> +	opp-625000000 {
> +		opp-hz = /bits/ 64 <625000000>;
> +		opp-microvolt = <800000>;
> +	};
> +	opp-1250000000 {
> +		opp-hz = /bits/ 64 <1250000000>;
> +		opp-microvolt = <1000000>;
> +	};
> +};
> +
> +&gmac0 {
> +	starfive,tx-use-rgmii-clk;
> +	assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
> +	assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
> +	status = "okay";
> +};
> +
> +&i2c0 {
> +	status = "okay";
> +};
> +
> +&mmc0 {
> +	bus-width = <4>;
> +	no-sdio;
> +	no-mmc;
> +	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_HIGH>;
> +	disable-wp;
> +	cap-sd-highspeed;
> +};
> +
> +&mmc1 {
> +	max-frequency = <50000000>;
> +	keep-power-in-suspend;
> +	non-removable;
> +};
> +
> +&pcie1 {
> +	enable-gpios = <&sysgpio 27 GPIO_ACTIVE_HIGH>;
> +	status = "okay";
> +};
> +
> +&phy0 {
> +	motorcomm,tx-clk-adj-enabled;
> +	motorcomm,tx-clk-100-inverted;
> +	motorcomm,tx-clk-1000-inverted;
> +	motorcomm,rx-clk-drv-microamp = <3970>;
> +	motorcomm,rx-data-drv-microamp = <2910>;
> +	rx-internal-delay-ps = <1500>;
> +	tx-internal-delay-ps = <1500>;
> +};
> +
> +&pwm {
> +	status = "okay";
> +};
> +
> +&spi0 {
> +	status = "okay";
> +};
> +
> +&syscrg {
> +	assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>, <1250000000>;
> +};

Circling back to a topic where I don't understand CPU clocks in hardware
design, but I have questions, I would want to see 8 divisions instead of
4 divisions (for both JH7110S and for JH7110). Similar for JH7110S here as:

&syscrg {
	assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>, <2500000000>;
};

and then in above &cpu_opp as:

&cpu_opp {
	opp-312500000 {
		opp-hz = /bits/ 64 <312500000>;
		opp-microvolt = <800000>;
	};
	opp-357000000 {
		opp-hz = /bits/ 64 <357000000>;
		opp-microvolt = <800000>;
	};
	opp-417000000 {
		opp-hz = /bits/ 64 <417000000>;
		opp-microvolt = <800000>;
	};
	opp-500000000 {
		opp-hz = /bits/ 64 <500000000>;
		opp-microvolt = <800000>;
	};
	opp-625000000 {
		opp-hz = /bits/ 64 <625000000>;
		opp-microvolt = <800000>;
	};
	opp-833000000 {
		opp-hz = /bits/ 64 <833000000>;
		opp-microvolt = <800000>;
	};
	opp-1250000000 {
		opp-hz = /bits/ 64 <1250000000>;
		opp-microvolt = <1000000>;
	};

	/* avoid division=1 2.5GHz omitted here, not supported by CPU */
};

What prevents this functionality I am asking about?  Specifically on
JH7110 the promotional block diagrams show 3.0GHz maximum (?  I think?
not sure but what else could this be?) so if that is true why do we not
divide down from that, avoiding divisions that are problematic?

-E

> +
> +&sysgpio {
> +	uart1_pins: uart1-0 {
> +		tx-pins {
> +			pinmux = <GPIOMUX(22, GPOUT_SYS_UART1_TX,
> +					      GPOEN_ENABLE,
> +					      GPI_NONE)>;
> +			bias-disable;
> +			drive-strength = <12>;
> +			input-disable;
> +			input-schmitt-disable;
> +			slew-rate = <0>;
> +		};
> +
> +		rx-pins {
> +			pinmux = <GPIOMUX(23, GPOUT_LOW,
> +					      GPOEN_DISABLE,
> +					      GPI_SYS_UART1_RX)>;
> +			bias-pull-up;
> +			drive-strength = <2>;
> +			input-enable;
> +			input-schmitt-enable;
> +			slew-rate = <0>;
> +		};
> +
> +		cts-pins {
> +			pinmux = <GPIOMUX(24, GPOUT_LOW,
> +					      GPOEN_DISABLE,
> +					      GPI_SYS_UART1_CTS)>;
> +			input-enable;
> +		};
> +
> +		rts-pins {
> +			pinmux = <GPIOMUX(25, GPOUT_SYS_UART1_RTS,
> +					      GPOEN_ENABLE,
> +					      GPI_NONE)>;
> +			input-enable;
> +		};
> +	};
> +
> +	usb0_pins: usb0-0 {
> +		power-pins {
> +			pinmux = <GPIOMUX(26, GPOUT_HIGH,
> +					      GPOEN_ENABLE,
> +					      GPI_NONE)>;
> +			input-disable;
> +		};
> +	};
> +};
> +
> +&uart1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&uart1_pins>;
> +	status = "okay";
> +};
> +
> +&usb0 {
> +	dr_mode = "host";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&usb0_pins>;
> +	status = "okay";
> +};
> +
> +&usb_cdns3 {
> +	phys = <&usbphy0>, <&pciephy0>;
> +	phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy";
> +};


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Re: [RFC 1/3] dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2 Lite board

[Icenowy Zheng]

在 2025-08-21星期四的 18:09 +0800，Hal Feng写道：
> Add device tree bindings for the StarFive JH7110S SoC
> and the VisionFive 2 Lite board equipped with it.
> 
> JH7110S SoC is an industrial SoC which can run at -40~85 degrees
> centigrade
> and up to 1.25GHz. Its CPU cores and peripherals are mostly similar
> to
> those of the JH7110 SoC.
> 
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
>  Documentation/devicetree/bindings/riscv/starfive.yaml | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml
> b/Documentation/devicetree/bindings/riscv/starfive.yaml
> index 7ef85174353d..a2952490709f 100644
> --- a/Documentation/devicetree/bindings/riscv/starfive.yaml
> +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
> @@ -33,6 +33,11 @@ properties:
>                - starfive,visionfive-2-v1.3b
>            - const: starfive,jh7110
>  
> +      - items:
> +          - enum:
> +              - starfive,visionfive-2-lite
> +          - const: starfive,jh7110s

I suggest adding starfive,jh7110 as a fallback here, as it's the SoC
best known to most softwares, and JH7110S shouldn't have any difference
to JH7110 other than binning.

> +
>  additionalProperties: true
>  
>  ...


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Re: [RFC 1/3] dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2 Lite board

[E Shattow]

On 8/24/25 10:14, Icenowy Zheng wrote:
> 在 2025-08-21星期四的 18:09 +0800，Hal Feng写道：
>> Add device tree bindings for the StarFive JH7110S SoC
>> and the VisionFive 2 Lite board equipped with it.
>>
>> JH7110S SoC is an industrial SoC which can run at -40~85 degrees
>> centigrade
>> and up to 1.25GHz. Its CPU cores and peripherals are mostly similar
>> to
>> those of the JH7110 SoC.
>>
>> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>> ---
>>  Documentation/devicetree/bindings/riscv/starfive.yaml | 5 +++++
>>  1 file changed, 5 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml
>> b/Documentation/devicetree/bindings/riscv/starfive.yaml
>> index 7ef85174353d..a2952490709f 100644
>> --- a/Documentation/devicetree/bindings/riscv/starfive.yaml
>> +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
>> @@ -33,6 +33,11 @@ properties:
>>                - starfive,visionfive-2-v1.3b
>>            - const: starfive,jh7110
>>  
>> +      - items:
>> +          - enum:
>> +              - starfive,visionfive-2-lite
>> +          - const: starfive,jh7110s
> 
> I suggest adding starfive,jh7110 as a fallback here, as it's the SoC
> best known to most softwares, and JH7110S shouldn't have any difference
> to JH7110 other than binning.
> 
>> +
>>  additionalProperties: true
>>  
>>  ...
> 

NAK, it is said the operating parameters of jh7110s are distinct from
jh7110. You would have to show that it is safe to operate the jh7110s
with the operating parameters of the jh7110. If anything this would be
the inverse, some jh711x (or even j71xx to include jh7100) common
description with fallback operating parameters? And to add this common
fallback with jh7100 (?), jh7110, jh7110s  -E

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RE: [RFC 3/3] riscv: dts: starfive: Add VisionFive 2 Lite board device tree

[Hal Feng]

> On 24.08.25 03:33, E Shattow wrote: 
> On 8/21/25 03:09, Hal Feng wrote:
> > VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S SoC.
> >
> > Board features:
> > - JH7110S SoC
> > - 2/4/8 GiB LPDDR4 DRAM
> > - AXP15060 PMIC
> > - 40 pin GPIO header
> > - 1x USB 3.0 host port
> > - 3x USB 2.0 host port
> > - 1x M.2 M-Key (size: 2242)
> > - 1x MicroSD slot (optional non-removable eMMC)
> > - 1x QSPI Flash
> > - 1x I2C EEPROM
> > - 1x 1Gbps Ethernet port
> > - SDIO-based Wi-Fi & UART-based Bluetooth
> > - 1x HDMI port
> > - 1x 2-lane DSI
> > - 1x 2-lane CSI
> >
> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> > ---
> >  arch/riscv/boot/dts/starfive/Makefile         |   2 +
> >  .../jh7110s-starfive-visionfive-2-lite.dts    | 152 ++++++++++++++++++
> >  2 files changed, 154 insertions(+)
> >  create mode 100644
> > arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dts
> >
> > diff --git a/arch/riscv/boot/dts/starfive/Makefile
> > b/arch/riscv/boot/dts/starfive/Makefile
> > index b3bb12f78e7d..7265c363e2a9 100644
> > --- a/arch/riscv/boot/dts/starfive/Makefile
> > +++ b/arch/riscv/boot/dts/starfive/Makefile
> > @@ -13,3 +13,5 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-
> mars.dtb
> >  dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-pine64-star64.dtb
> >  dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
> >  dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
> > +
> > +dtb-$(CONFIG_ARCH_STARFIVE) += jh7110s-starfive-visionfive-2-lite.dtb
> > diff --git
> > a/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dts
> > b/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dts
> > new file mode 100644
> > index 000000000000..a0cb9912eb80
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.
> > +++ dts
> > @@ -0,0 +1,152 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > +/*
> > + * Copyright (C) 2025 StarFive Technology Co., Ltd.
> > + * Copyright (C) 2025 Hal Feng <hal.feng@starfivetech.com>  */
> > +
> > +/dts-v1/;
> > +#include "jh7110-common.dtsi"
> > +
> > +/ {
> > +	model = "StarFive VisionFive 2 Lite";
> > +	compatible = "starfive,visionfive-2-lite", "starfive,jh7110s"; };
> > +
> > +&cpu_opp {
> > +	opp-312500000 {
> > +		opp-hz = /bits/ 64 <312500000>;
> > +		opp-microvolt = <800000>;
> > +	};
> > +	opp-417000000 {
> > +		opp-hz = /bits/ 64 <417000000>;
> > +		opp-microvolt = <800000>;
> > +	};
> > +	opp-625000000 {
> > +		opp-hz = /bits/ 64 <625000000>;
> > +		opp-microvolt = <800000>;
> > +	};
> > +	opp-1250000000 {
> > +		opp-hz = /bits/ 64 <1250000000>;
> > +		opp-microvolt = <1000000>;
> > +	};
> > +};
> > +
> > +&gmac0 {
> > +	starfive,tx-use-rgmii-clk;
> > +	assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
> > +	assigned-clock-parents = <&aoncrg
> JH7110_AONCLK_GMAC0_RMII_RTX>;
> > +	status = "okay";
> > +};
> > +
> > +&i2c0 {
> > +	status = "okay";
> > +};
> > +
> > +&mmc0 {
> > +	bus-width = <4>;
> > +	no-sdio;
> > +	no-mmc;
> > +	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_HIGH>;
> > +	disable-wp;
> > +	cap-sd-highspeed;
> > +};
> > +
> > +&mmc1 {
> > +	max-frequency = <50000000>;
> > +	keep-power-in-suspend;
> > +	non-removable;
> > +};
> > +
> > +&pcie1 {
> > +	enable-gpios = <&sysgpio 27 GPIO_ACTIVE_HIGH>;
> > +	status = "okay";
> > +};
> > +
> > +&phy0 {
> > +	motorcomm,tx-clk-adj-enabled;
> > +	motorcomm,tx-clk-100-inverted;
> > +	motorcomm,tx-clk-1000-inverted;
> > +	motorcomm,rx-clk-drv-microamp = <3970>;
> > +	motorcomm,rx-data-drv-microamp = <2910>;
> > +	rx-internal-delay-ps = <1500>;
> > +	tx-internal-delay-ps = <1500>;
> > +};
> > +
> > +&pwm {
> > +	status = "okay";
> > +};
> > +
> > +&spi0 {
> > +	status = "okay";
> > +};
> > +
> > +&syscrg {
> > +	assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>,
> > +<1250000000>; };
> 
> Circling back to a topic where I don't understand CPU clocks in hardware
> design, but I have questions, I would want to see 8 divisions instead of
> 4 divisions (for both JH7110S and for JH7110). Similar for JH7110S here as:
> 
> &syscrg {
> 	assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>,
> <2500000000>; };
> 
> and then in above &cpu_opp as:
> 
> &cpu_opp {
> 	opp-312500000 {
> 		opp-hz = /bits/ 64 <312500000>;
> 		opp-microvolt = <800000>;
> 	};
> 	opp-357000000 {
> 		opp-hz = /bits/ 64 <357000000>;
> 		opp-microvolt = <800000>;
> 	};
> 	opp-417000000 {
> 		opp-hz = /bits/ 64 <417000000>;
> 		opp-microvolt = <800000>;
> 	};
> 	opp-500000000 {
> 		opp-hz = /bits/ 64 <500000000>;
> 		opp-microvolt = <800000>;
> 	};
> 	opp-625000000 {
> 		opp-hz = /bits/ 64 <625000000>;
> 		opp-microvolt = <800000>;
> 	};
> 	opp-833000000 {
> 		opp-hz = /bits/ 64 <833000000>;
> 		opp-microvolt = <800000>;
> 	};
> 	opp-1250000000 {
> 		opp-hz = /bits/ 64 <1250000000>;
> 		opp-microvolt = <1000000>;
> 	};
> 
> 	/* avoid division=1 2.5GHz omitted here, not supported by CPU */ };
> 
> What prevents this functionality I am asking about?  Specifically on
> JH7110 the promotional block diagrams show 3.0GHz maximum (?  I think?
> not sure but what else could this be?) so if that is true why do we not divide
> down from that, avoiding divisions that are problematic?

It is a good idea and I tested your code successfully on VF2 Lite.
But we have not done stress tests for this and I am not sure whether it will break the chip stability.
Anyway, it is a good suggestion and more tests should be run later.

Best regards,
Hal

> > +
> > +&sysgpio {
> > +	uart1_pins: uart1-0 {
> > +		tx-pins {
> > +			pinmux = <GPIOMUX(22, GPOUT_SYS_UART1_TX,
> > +					      GPOEN_ENABLE,
> > +					      GPI_NONE)>;
> > +			bias-disable;
> > +			drive-strength = <12>;
> > +			input-disable;
> > +			input-schmitt-disable;
> > +			slew-rate = <0>;
> > +		};
> > +
> > +		rx-pins {
> > +			pinmux = <GPIOMUX(23, GPOUT_LOW,
> > +					      GPOEN_DISABLE,
> > +					      GPI_SYS_UART1_RX)>;
> > +			bias-pull-up;
> > +			drive-strength = <2>;
> > +			input-enable;
> > +			input-schmitt-enable;
> > +			slew-rate = <0>;
> > +		};
> > +
> > +		cts-pins {
> > +			pinmux = <GPIOMUX(24, GPOUT_LOW,
> > +					      GPOEN_DISABLE,
> > +					      GPI_SYS_UART1_CTS)>;
> > +			input-enable;
> > +		};
> > +
> > +		rts-pins {
> > +			pinmux = <GPIOMUX(25, GPOUT_SYS_UART1_RTS,
> > +					      GPOEN_ENABLE,
> > +					      GPI_NONE)>;
> > +			input-enable;
> > +		};
> > +	};
> > +
> > +	usb0_pins: usb0-0 {
> > +		power-pins {
> > +			pinmux = <GPIOMUX(26, GPOUT_HIGH,
> > +					      GPOEN_ENABLE,
> > +					      GPI_NONE)>;
> > +			input-disable;
> > +		};
> > +	};
> > +};
> > +
> > +&uart1 {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&uart1_pins>;
> > +	status = "okay";
> > +};
> > +
> > +&usb0 {
> > +	dr_mode = "host";
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&usb0_pins>;
> > +	status = "okay";
> > +};
> > +
> > +&usb_cdns3 {
> > +	phys = <&usbphy0>, <&pciephy0>;
> > +	phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy"; };

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