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Thu, 14 Sep 2023 10:29:20 -0700 (PDT) Date: Thu, 14 Sep 2023 13:29:18 -0400 From: Charlie Jenkins To: Conor Dooley Subject: Re: [PATCH v4 4/5] riscv: Vector checksum library Message-ID: References: <20230911-optimize_checksum-v4-0-77cc2ad9e9d7@rivosinc.com> <20230911-optimize_checksum-v4-4-77cc2ad9e9d7@rivosinc.com> <20230914-pennant-obligate-db3adf056281@wendy> <20230914-hardiness-uninjured-6818bfb40b4f@spud> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230914-hardiness-uninjured-6818bfb40b4f@spud> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230914_102924_754428_417F5606 X-CRM114-Status: GOOD ( 35.15 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Albert Ou , linux-kernel@vger.kernel.org, Conor Dooley , David Laight , Palmer Dabbelt , Paul Walmsley , linux-riscv@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, Sep 14, 2023 at 05:29:29PM +0100, Conor Dooley wrote: > On Thu, Sep 14, 2023 at 12:14:16PM -0400, Charlie Jenkins wrote: > > On Thu, Sep 14, 2023 at 01:46:29PM +0100, Conor Dooley wrote: > > > On Mon, Sep 11, 2023 at 03:57:14PM -0700, Charlie Jenkins wrote: > > > > This patch is not ready for merge as vector support in the kernel is > > > > limited. However, the code has been tested in QEMU so the algorithms > > > > do work. This code requires the kernel to be compiled with C vector > > > > support, but that is not yet possible. It is written in assembly > > > > rather than using the GCC vector instrinsics because they did not > > > > provide optimal code. > > > > > > > > Signed-off-by: Charlie Jenkins > > > > --- > > > > arch/riscv/lib/csum.c | 92 +++++++++++++++++++++++++++++++++++++++++++++++++++ > > > > 1 file changed, 92 insertions(+) > > > > > > > > diff --git a/arch/riscv/lib/csum.c b/arch/riscv/lib/csum.c > > > > index 47d98c51bab2..eb4596fc7f5b 100644 > > > > --- a/arch/riscv/lib/csum.c > > > > +++ b/arch/riscv/lib/csum.c > > > > @@ -12,6 +12,10 @@ > > > > > > > > #include > > > > > > > > +#ifdef CONFIG_RISCV_ISA_V > > > > +#include > > > > > > What actually includes this header, I don't see it in either Andy's > > > in-kernel vector series or Bjorn's blake2 one. > > > Can you link to the pre-requisites in your cover letter please. > > > > > > Thanks, > > > Conor. > > > > It is defined here: > > https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/main/doc/rvv-intrinsic-spec.adoc. > > The header is for the vector intrinsics that are supported by llvm and > > gcc. > > Well, whatever you're doing with it does not work, producing 3600 or so > fatal errors during compilation, all saying: > ../arch/riscv/include/asm/checksum.h:14:10: fatal error: riscv_vector.h: No such file or directory > > Do you have some makefile hack somewhere that's not part of this > patchset? Also, I'm dumb, but can you show me where are the actual > intrinsics are being used in this patch anyway? I just seem some > types & asm. > > Thanks, > Conor. > Intrinsics are needed for the vector types. Vector types are needed to get the inline asm to select vector registers at compile time. I could manually select vector registers to use but that is not ideal. In order to get this to work, vector has to be enabled in the compiler. This patch will not compile right now, but since people are working on vector I was hoping that it would be possible in the future. Palmer recommended that I just put up this patch for now since I had the code, but only the non-vector versions should be candidates for release for now. - Charlie _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv