* [PATCH v3 1/3] riscv: Improve PTDUMP to show RSW with non-zero value
@ 2023-09-20 3:55 Yu Chien Peter Lin
2023-09-20 3:55 ` [PATCH v3 2/3] riscv: Introduce PBMT field to PTDUMP Yu Chien Peter Lin
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: Yu Chien Peter Lin @ 2023-09-20 3:55 UTC (permalink / raw)
To: paul.walmsley, palmer, aou, david, akpm, alexghiti, bjorn,
linux-riscv, linux-kernel
Cc: conor.dooley, Yu Chien Peter Lin
RSW field can be used to encode 2 bits of software
defined information. Currently, PTDUMP only prints
"RSW" when its value is 1 or 3.
To fix this issue and improve the debugging experience
with PTDUMP, we redefine _PAGE_SPECIAL to its original
value and use _PAGE_SOFT as the RSW mask, allow it to
print the RSW with any non-zero value.
This patch also removes the val from the struct prot_bits
as it is no longer needed.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
---
Changes v1 -> v2
- Redefine _PAGE_SPECIAL to (1 << 8)
Changes v2 -> v3
- Add commet for _PAGE_SPECIAL
- Add ".." when RSW field is clear
- Fix unbalanced braces warning
---
arch/riscv/include/asm/pgtable-bits.h | 4 +--
arch/riscv/mm/ptdump.c | 35 ++++++++++++---------------
2 files changed, 17 insertions(+), 22 deletions(-)
diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
index f896708e8331..179bd4afece4 100644
--- a/arch/riscv/include/asm/pgtable-bits.h
+++ b/arch/riscv/include/asm/pgtable-bits.h
@@ -16,9 +16,9 @@
#define _PAGE_GLOBAL (1 << 5) /* Global */
#define _PAGE_ACCESSED (1 << 6) /* Set by hardware on any access */
#define _PAGE_DIRTY (1 << 7) /* Set by hardware on any write */
-#define _PAGE_SOFT (1 << 8) /* Reserved for software */
+#define _PAGE_SOFT (3 << 8) /* Reserved for software */
-#define _PAGE_SPECIAL _PAGE_SOFT
+#define _PAGE_SPECIAL (1 << 8) /* RSW: 0x1 */
#define _PAGE_TABLE _PAGE_PRESENT
/*
diff --git a/arch/riscv/mm/ptdump.c b/arch/riscv/mm/ptdump.c
index 20a9f991a6d7..57a0926c6627 100644
--- a/arch/riscv/mm/ptdump.c
+++ b/arch/riscv/mm/ptdump.c
@@ -129,7 +129,6 @@ static struct ptd_mm_info efi_ptd_info = {
/* Page Table Entry */
struct prot_bits {
u64 mask;
- u64 val;
const char *set;
const char *clear;
};
@@ -137,47 +136,38 @@ struct prot_bits {
static const struct prot_bits pte_bits[] = {
{
.mask = _PAGE_SOFT,
- .val = _PAGE_SOFT,
- .set = "RSW",
- .clear = " ",
+ .set = "RSW(%d)",
+ .clear = " .. ",
}, {
.mask = _PAGE_DIRTY,
- .val = _PAGE_DIRTY,
.set = "D",
.clear = ".",
}, {
.mask = _PAGE_ACCESSED,
- .val = _PAGE_ACCESSED,
.set = "A",
.clear = ".",
}, {
.mask = _PAGE_GLOBAL,
- .val = _PAGE_GLOBAL,
.set = "G",
.clear = ".",
}, {
.mask = _PAGE_USER,
- .val = _PAGE_USER,
.set = "U",
.clear = ".",
}, {
.mask = _PAGE_EXEC,
- .val = _PAGE_EXEC,
.set = "X",
.clear = ".",
}, {
.mask = _PAGE_WRITE,
- .val = _PAGE_WRITE,
.set = "W",
.clear = ".",
}, {
.mask = _PAGE_READ,
- .val = _PAGE_READ,
.set = "R",
.clear = ".",
}, {
.mask = _PAGE_PRESENT,
- .val = _PAGE_PRESENT,
.set = "V",
.clear = ".",
}
@@ -208,15 +198,20 @@ static void dump_prot(struct pg_state *st)
unsigned int i;
for (i = 0; i < ARRAY_SIZE(pte_bits); i++) {
- const char *s;
-
- if ((st->current_prot & pte_bits[i].mask) == pte_bits[i].val)
- s = pte_bits[i].set;
- else
- s = pte_bits[i].clear;
+ char s[7];
+ unsigned long val;
+
+ val = st->current_prot & pte_bits[i].mask;
+ if (val) {
+ if (pte_bits[i].mask == _PAGE_SOFT)
+ sprintf(s, pte_bits[i].set, val >> 8);
+ else
+ sprintf(s, "%s", pte_bits[i].set);
+ } else {
+ sprintf(s, "%s", pte_bits[i].clear);
+ }
- if (s)
- pt_dump_seq_printf(st->seq, " %s", s);
+ pt_dump_seq_printf(st->seq, " %s", s);
}
}
--
2.34.1
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3 2/3] riscv: Introduce PBMT field to PTDUMP
2023-09-20 3:55 [PATCH v3 1/3] riscv: Improve PTDUMP to show RSW with non-zero value Yu Chien Peter Lin
@ 2023-09-20 3:55 ` Yu Chien Peter Lin
2023-09-20 9:12 ` Alexandre Ghiti
2023-09-20 3:55 ` [PATCH v3 3/3] riscv: Introduce NAPOT " Yu Chien Peter Lin
` (2 subsequent siblings)
3 siblings, 1 reply; 8+ messages in thread
From: Yu Chien Peter Lin @ 2023-09-20 3:55 UTC (permalink / raw)
To: paul.walmsley, palmer, aou, david, akpm, alexghiti, bjorn,
linux-riscv, linux-kernel
Cc: conor.dooley, Yu Chien Peter Lin
This patch introduces the PBMT field to the PTDUMP, so it can
display the memory attributes for NC or IO.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
---
Changes v1 -> v2
- no change
Changes v2 -> v3
- Add ".." when PBMT field is clear
---
arch/riscv/mm/ptdump.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/riscv/mm/ptdump.c b/arch/riscv/mm/ptdump.c
index 57a0926c6627..13997cf3fe36 100644
--- a/arch/riscv/mm/ptdump.c
+++ b/arch/riscv/mm/ptdump.c
@@ -135,6 +135,12 @@ struct prot_bits {
static const struct prot_bits pte_bits[] = {
{
+#ifdef CONFIG_64BIT
+ .mask = _PAGE_MTMASK_SVPBMT,
+ .set = "MT(%s)",
+ .clear = " .. ",
+ }, {
+#endif
.mask = _PAGE_SOFT,
.set = "RSW(%d)",
.clear = " .. ",
@@ -205,6 +211,16 @@ static void dump_prot(struct pg_state *st)
if (val) {
if (pte_bits[i].mask == _PAGE_SOFT)
sprintf(s, pte_bits[i].set, val >> 8);
+#ifdef CONFIG_64BIT
+ else if (pte_bits[i].mask == _PAGE_MTMASK_SVPBMT) {
+ if (val == _PAGE_NOCACHE_SVPBMT)
+ sprintf(s, pte_bits[i].set, "NC");
+ else if (val == _PAGE_IO_SVPBMT)
+ sprintf(s, pte_bits[i].set, "IO");
+ else
+ sprintf(s, pte_bits[i].set, "??");
+ }
+#endif
else
sprintf(s, "%s", pte_bits[i].set);
} else {
--
2.34.1
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3 3/3] riscv: Introduce NAPOT field to PTDUMP
2023-09-20 3:55 [PATCH v3 1/3] riscv: Improve PTDUMP to show RSW with non-zero value Yu Chien Peter Lin
2023-09-20 3:55 ` [PATCH v3 2/3] riscv: Introduce PBMT field to PTDUMP Yu Chien Peter Lin
@ 2023-09-20 3:55 ` Yu Chien Peter Lin
2023-09-20 9:14 ` Alexandre Ghiti
2023-09-20 9:10 ` [PATCH v3 1/3] riscv: Improve PTDUMP to show RSW with non-zero value Alexandre Ghiti
2023-09-20 9:55 ` Conor Dooley
3 siblings, 1 reply; 8+ messages in thread
From: Yu Chien Peter Lin @ 2023-09-20 3:55 UTC (permalink / raw)
To: paul.walmsley, palmer, aou, david, akpm, alexghiti, bjorn,
linux-riscv, linux-kernel
Cc: conor.dooley, Yu Chien Peter Lin
This patch introduces the NAPOT field to PTDUMP, allowing it
to display the letter "N" for pages that have the 63rd bit set.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
---
Changes v1 -> v3
- no change
---
arch/riscv/mm/ptdump.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/riscv/mm/ptdump.c b/arch/riscv/mm/ptdump.c
index 13997cf3fe36..b71f08b91e53 100644
--- a/arch/riscv/mm/ptdump.c
+++ b/arch/riscv/mm/ptdump.c
@@ -136,6 +136,10 @@ struct prot_bits {
static const struct prot_bits pte_bits[] = {
{
#ifdef CONFIG_64BIT
+ .mask = _PAGE_NAPOT,
+ .set = "N",
+ .clear = ".",
+ }, {
.mask = _PAGE_MTMASK_SVPBMT,
.set = "MT(%s)",
.clear = " .. ",
--
2.34.1
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v3 1/3] riscv: Improve PTDUMP to show RSW with non-zero value
2023-09-20 3:55 [PATCH v3 1/3] riscv: Improve PTDUMP to show RSW with non-zero value Yu Chien Peter Lin
2023-09-20 3:55 ` [PATCH v3 2/3] riscv: Introduce PBMT field to PTDUMP Yu Chien Peter Lin
2023-09-20 3:55 ` [PATCH v3 3/3] riscv: Introduce NAPOT " Yu Chien Peter Lin
@ 2023-09-20 9:10 ` Alexandre Ghiti
2023-09-20 9:55 ` Conor Dooley
3 siblings, 0 replies; 8+ messages in thread
From: Alexandre Ghiti @ 2023-09-20 9:10 UTC (permalink / raw)
To: Yu Chien Peter Lin, paul.walmsley, palmer, aou, david, akpm,
alexghiti, bjorn, linux-riscv, linux-kernel
Cc: conor.dooley
Hi,
On 20/09/2023 05:55, Yu Chien Peter Lin wrote:
> RSW field can be used to encode 2 bits of software
> defined information. Currently, PTDUMP only prints
> "RSW" when its value is 1 or 3.
>
> To fix this issue and improve the debugging experience
> with PTDUMP, we redefine _PAGE_SPECIAL to its original
> value and use _PAGE_SOFT as the RSW mask, allow it to
> print the RSW with any non-zero value.
>
> This patch also removes the val from the struct prot_bits
> as it is no longer needed.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> ---
> Changes v1 -> v2
> - Redefine _PAGE_SPECIAL to (1 << 8)
> Changes v2 -> v3
> - Add commet for _PAGE_SPECIAL
> - Add ".." when RSW field is clear
> - Fix unbalanced braces warning
> ---
> arch/riscv/include/asm/pgtable-bits.h | 4 +--
> arch/riscv/mm/ptdump.c | 35 ++++++++++++---------------
> 2 files changed, 17 insertions(+), 22 deletions(-)
>
> diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
> index f896708e8331..179bd4afece4 100644
> --- a/arch/riscv/include/asm/pgtable-bits.h
> +++ b/arch/riscv/include/asm/pgtable-bits.h
> @@ -16,9 +16,9 @@
> #define _PAGE_GLOBAL (1 << 5) /* Global */
> #define _PAGE_ACCESSED (1 << 6) /* Set by hardware on any access */
> #define _PAGE_DIRTY (1 << 7) /* Set by hardware on any write */
> -#define _PAGE_SOFT (1 << 8) /* Reserved for software */
> +#define _PAGE_SOFT (3 << 8) /* Reserved for software */
>
> -#define _PAGE_SPECIAL _PAGE_SOFT
> +#define _PAGE_SPECIAL (1 << 8) /* RSW: 0x1 */
> #define _PAGE_TABLE _PAGE_PRESENT
>
> /*
> diff --git a/arch/riscv/mm/ptdump.c b/arch/riscv/mm/ptdump.c
> index 20a9f991a6d7..57a0926c6627 100644
> --- a/arch/riscv/mm/ptdump.c
> +++ b/arch/riscv/mm/ptdump.c
> @@ -129,7 +129,6 @@ static struct ptd_mm_info efi_ptd_info = {
> /* Page Table Entry */
> struct prot_bits {
> u64 mask;
> - u64 val;
> const char *set;
> const char *clear;
> };
> @@ -137,47 +136,38 @@ struct prot_bits {
> static const struct prot_bits pte_bits[] = {
> {
> .mask = _PAGE_SOFT,
> - .val = _PAGE_SOFT,
> - .set = "RSW",
> - .clear = " ",
> + .set = "RSW(%d)",
> + .clear = " .. ",
> }, {
> .mask = _PAGE_DIRTY,
> - .val = _PAGE_DIRTY,
> .set = "D",
> .clear = ".",
> }, {
> .mask = _PAGE_ACCESSED,
> - .val = _PAGE_ACCESSED,
> .set = "A",
> .clear = ".",
> }, {
> .mask = _PAGE_GLOBAL,
> - .val = _PAGE_GLOBAL,
> .set = "G",
> .clear = ".",
> }, {
> .mask = _PAGE_USER,
> - .val = _PAGE_USER,
> .set = "U",
> .clear = ".",
> }, {
> .mask = _PAGE_EXEC,
> - .val = _PAGE_EXEC,
> .set = "X",
> .clear = ".",
> }, {
> .mask = _PAGE_WRITE,
> - .val = _PAGE_WRITE,
> .set = "W",
> .clear = ".",
> }, {
> .mask = _PAGE_READ,
> - .val = _PAGE_READ,
> .set = "R",
> .clear = ".",
> }, {
> .mask = _PAGE_PRESENT,
> - .val = _PAGE_PRESENT,
> .set = "V",
> .clear = ".",
> }
> @@ -208,15 +198,20 @@ static void dump_prot(struct pg_state *st)
> unsigned int i;
>
> for (i = 0; i < ARRAY_SIZE(pte_bits); i++) {
> - const char *s;
> -
> - if ((st->current_prot & pte_bits[i].mask) == pte_bits[i].val)
> - s = pte_bits[i].set;
> - else
> - s = pte_bits[i].clear;
> + char s[7];
> + unsigned long val;
> +
> + val = st->current_prot & pte_bits[i].mask;
> + if (val) {
> + if (pte_bits[i].mask == _PAGE_SOFT)
> + sprintf(s, pte_bits[i].set, val >> 8);
> + else
> + sprintf(s, "%s", pte_bits[i].set);
> + } else {
> + sprintf(s, "%s", pte_bits[i].clear);
> + }
>
> - if (s)
> - pt_dump_seq_printf(st->seq, " %s", s);
> + pt_dump_seq_printf(st->seq, " %s", s);
> }
> }
>
You can add:
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Tested-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Thanks!
Alex
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v3 2/3] riscv: Introduce PBMT field to PTDUMP
2023-09-20 3:55 ` [PATCH v3 2/3] riscv: Introduce PBMT field to PTDUMP Yu Chien Peter Lin
@ 2023-09-20 9:12 ` Alexandre Ghiti
0 siblings, 0 replies; 8+ messages in thread
From: Alexandre Ghiti @ 2023-09-20 9:12 UTC (permalink / raw)
To: Yu Chien Peter Lin, paul.walmsley, palmer, aou, david, akpm,
alexghiti, bjorn, linux-riscv, linux-kernel
Cc: conor.dooley
On 20/09/2023 05:55, Yu Chien Peter Lin wrote:
> This patch introduces the PBMT field to the PTDUMP, so it can
> display the memory attributes for NC or IO.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> ---
> Changes v1 -> v2
> - no change
> Changes v2 -> v3
> - Add ".." when PBMT field is clear
> ---
> arch/riscv/mm/ptdump.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/riscv/mm/ptdump.c b/arch/riscv/mm/ptdump.c
> index 57a0926c6627..13997cf3fe36 100644
> --- a/arch/riscv/mm/ptdump.c
> +++ b/arch/riscv/mm/ptdump.c
> @@ -135,6 +135,12 @@ struct prot_bits {
>
> static const struct prot_bits pte_bits[] = {
> {
> +#ifdef CONFIG_64BIT
> + .mask = _PAGE_MTMASK_SVPBMT,
> + .set = "MT(%s)",
> + .clear = " .. ",
> + }, {
> +#endif
> .mask = _PAGE_SOFT,
> .set = "RSW(%d)",
> .clear = " .. ",
> @@ -205,6 +211,16 @@ static void dump_prot(struct pg_state *st)
> if (val) {
> if (pte_bits[i].mask == _PAGE_SOFT)
> sprintf(s, pte_bits[i].set, val >> 8);
> +#ifdef CONFIG_64BIT
> + else if (pte_bits[i].mask == _PAGE_MTMASK_SVPBMT) {
> + if (val == _PAGE_NOCACHE_SVPBMT)
> + sprintf(s, pte_bits[i].set, "NC");
> + else if (val == _PAGE_IO_SVPBMT)
> + sprintf(s, pte_bits[i].set, "IO");
> + else
> + sprintf(s, pte_bits[i].set, "??");
> + }
> +#endif
> else
> sprintf(s, "%s", pte_bits[i].set);
> } else {
You can add:
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Tested-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Thanks!
Alex
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v3 3/3] riscv: Introduce NAPOT field to PTDUMP
2023-09-20 3:55 ` [PATCH v3 3/3] riscv: Introduce NAPOT " Yu Chien Peter Lin
@ 2023-09-20 9:14 ` Alexandre Ghiti
0 siblings, 0 replies; 8+ messages in thread
From: Alexandre Ghiti @ 2023-09-20 9:14 UTC (permalink / raw)
To: Yu Chien Peter Lin, paul.walmsley, palmer, aou, david, akpm,
alexghiti, bjorn, linux-riscv, linux-kernel
Cc: conor.dooley
On 20/09/2023 05:55, Yu Chien Peter Lin wrote:
> This patch introduces the NAPOT field to PTDUMP, allowing it
> to display the letter "N" for pages that have the 63rd bit set.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> ---
> Changes v1 -> v3
> - no change
> ---
> arch/riscv/mm/ptdump.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/riscv/mm/ptdump.c b/arch/riscv/mm/ptdump.c
> index 13997cf3fe36..b71f08b91e53 100644
> --- a/arch/riscv/mm/ptdump.c
> +++ b/arch/riscv/mm/ptdump.c
> @@ -136,6 +136,10 @@ struct prot_bits {
> static const struct prot_bits pte_bits[] = {
> {
> #ifdef CONFIG_64BIT
> + .mask = _PAGE_NAPOT,
> + .set = "N",
> + .clear = ".",
> + }, {
> .mask = _PAGE_MTMASK_SVPBMT,
> .set = "MT(%s)",
> .clear = " .. ",
Nice to see that we actually transparently use napot mappings:
---[ PCI I/O start ]---
0xffff8d7fff000000-0xffff8d7fff010000 0x0000000003000000 64K PTE N
.. .. D A G . . W R V
You can add:
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Tested-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Thanks for the series, really appreciated!
Alex
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v3 1/3] riscv: Improve PTDUMP to show RSW with non-zero value
2023-09-20 3:55 [PATCH v3 1/3] riscv: Improve PTDUMP to show RSW with non-zero value Yu Chien Peter Lin
` (2 preceding siblings ...)
2023-09-20 9:10 ` [PATCH v3 1/3] riscv: Improve PTDUMP to show RSW with non-zero value Alexandre Ghiti
@ 2023-09-20 9:55 ` Conor Dooley
2023-09-21 1:40 ` Yu-Chien Peter Lin
3 siblings, 1 reply; 8+ messages in thread
From: Conor Dooley @ 2023-09-20 9:55 UTC (permalink / raw)
To: Yu Chien Peter Lin
Cc: paul.walmsley, palmer, aou, david, akpm, alexghiti, bjorn,
linux-riscv, linux-kernel
[-- Attachment #1.1: Type: text/plain, Size: 613 bytes --]
On Wed, Sep 20, 2023 at 11:55:20AM +0800, Yu Chien Peter Lin wrote:
> RSW field can be used to encode 2 bits of software
> defined information. Currently, PTDUMP only prints
> "RSW" when its value is 1 or 3.
>
> To fix this issue and improve the debugging experience
> with PTDUMP, we redefine _PAGE_SPECIAL to its original
> value and use _PAGE_SOFT as the RSW mask, allow it to
> print the RSW with any non-zero value.
>
> This patch also removes the val from the struct prot_bits
> as it is no longer needed.
>
Could you please add cover letters to multi-patch patchsets?
Thanks,
Conor.
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v3 1/3] riscv: Improve PTDUMP to show RSW with non-zero value
2023-09-20 9:55 ` Conor Dooley
@ 2023-09-21 1:40 ` Yu-Chien Peter Lin
0 siblings, 0 replies; 8+ messages in thread
From: Yu-Chien Peter Lin @ 2023-09-21 1:40 UTC (permalink / raw)
To: Conor Dooley
Cc: paul.walmsley, palmer, aou, david, akpm, alexghiti, bjorn,
linux-riscv, linux-kernel
Hi Conor,
On Wed, Sep 20, 2023 at 10:55:30AM +0100, Conor Dooley wrote:
> On Wed, Sep 20, 2023 at 11:55:20AM +0800, Yu Chien Peter Lin wrote:
> > RSW field can be used to encode 2 bits of software
> > defined information. Currently, PTDUMP only prints
> > "RSW" when its value is 1 or 3.
> >
> > To fix this issue and improve the debugging experience
> > with PTDUMP, we redefine _PAGE_SPECIAL to its original
> > value and use _PAGE_SOFT as the RSW mask, allow it to
> > print the RSW with any non-zero value.
> >
> > This patch also removes the val from the struct prot_bits
> > as it is no longer needed.
> >
>
> Could you please add cover letters to multi-patch patchsets?
>
> Thanks,
> Conor.
Sure, will do.
Regards,
Peter Lin
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^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2023-09-21 1:41 UTC | newest]
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2023-09-20 3:55 [PATCH v3 1/3] riscv: Improve PTDUMP to show RSW with non-zero value Yu Chien Peter Lin
2023-09-20 3:55 ` [PATCH v3 2/3] riscv: Introduce PBMT field to PTDUMP Yu Chien Peter Lin
2023-09-20 9:12 ` Alexandre Ghiti
2023-09-20 3:55 ` [PATCH v3 3/3] riscv: Introduce NAPOT " Yu Chien Peter Lin
2023-09-20 9:14 ` Alexandre Ghiti
2023-09-20 9:10 ` [PATCH v3 1/3] riscv: Improve PTDUMP to show RSW with non-zero value Alexandre Ghiti
2023-09-20 9:55 ` Conor Dooley
2023-09-21 1:40 ` Yu-Chien Peter Lin
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