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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Oct 02, 2023 at 01:09:38PM +0100, Conor Dooley wrote: > On Sat, Sep 30, 2023 at 08:39:36PM +0800, Jisheng Zhang wrote: > > Add initial device tree for the CV1800B RISC-V SoC by SOPHGO. > > > > Signed-off-by: Jisheng Zhang > > --- > > arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 117 ++++++++++++++++++++++++ > > 1 file changed, 117 insertions(+) > > create mode 100644 arch/riscv/boot/dts/sophgo/cv1800b.dtsi > > > > diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > > new file mode 100644 > > index 000000000000..8829bebaa017 > > --- /dev/null > > +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > > @@ -0,0 +1,117 @@ > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > > +/* > > + * Copyright (C) 2023 Jisheng Zhang > > + */ > > + > > +#include > > + > > +/ { > > + compatible = "sophgo,cv1800b"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + cpus: cpus { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + timebase-frequency = <25000000>; > > + > > + cpu0: cpu@0 { > > + compatible = "thead,c906", "riscv"; > > + device_type = "cpu"; > > + reg = <0>; > > + d-cache-block-size = <64>; > > + d-cache-sets = <512>; > > + d-cache-size = <65536>; > > + i-cache-block-size = <64>; > > + i-cache-sets = <128>; > > + i-cache-size = <32768>; > > + mmu-type = "riscv,sv39"; > > + riscv,isa = "rv64imafdc"; > > + riscv,isa-base = "rv64i"; > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", > > + "zifencei", "zihpm"; > > + > > + cpu0_intc: interrupt-controller { > > + compatible = "riscv,cpu-intc"; > > + interrupt-controller; > > + #address-cells = <0>; > > + #interrupt-cells = <1>; > > + }; > > + }; > > + }; > > + > > + osc: oscillator { > > + compatible = "fixed-clock"; > > + clock-output-names = "osc_25m"; > > + #clock-cells = <0>; > > + }; > > Is this a stub that will later be replaced by a real clock controller > node, or is this actually a fixed oscillator? If it is the former, could Hi Conor, This is a real 25MHZ oscillator. Thanks _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv