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Mon, 25 Sep 2023 11:12:45 -0700 (PDT) Date: Mon, 25 Sep 2023 11:12:42 -0700 From: Charlie Jenkins To: Anup Patel Cc: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Shuah Khan , Andrew Jones , Mayuresh Chitale , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH v2 2/9] RISC-V: Detect XVentanaCondOps from ISA string Message-ID: References: <20230925133859.1735879-1-apatel@ventanamicro.com> <20230925133859.1735879-3-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230925_111248_811948_83A3C61C X-CRM114-Status: GOOD ( 28.71 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Sep 25, 2023 at 10:48:11AM -0700, Charlie Jenkins wrote: > On Mon, Sep 25, 2023 at 07:08:52PM +0530, Anup Patel wrote: > > The Veyron-V1 CPU supports custom conditional arithmetic and > > conditional-select/move operations referred to as XVentanaCondOps > > extension. In fact, QEMU RISC-V also has support for emulating > > XVentanaCondOps extension. > > > > Let us detect XVentanaCondOps extension from ISA string available > > through DT or ACPI. > > > > Signed-off-by: Anup Patel > > Reviewed-by: Andrew Jones > > --- > > arch/riscv/include/asm/hwcap.h | 1 + > > arch/riscv/kernel/cpufeature.c | 1 + > > 2 files changed, 2 insertions(+) > > > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > > index 0f520f7d058a..b7efe9e2fa89 100644 > > --- a/arch/riscv/include/asm/hwcap.h > > +++ b/arch/riscv/include/asm/hwcap.h > > @@ -59,6 +59,7 @@ > > #define RISCV_ISA_EXT_ZIFENCEI 41 > > #define RISCV_ISA_EXT_ZIHPM 42 > > #define RISCV_ISA_EXT_SMSTATEEN 43 > > +#define RISCV_ISA_EXT_XVENTANACONDOPS 44 > > > > #define RISCV_ISA_EXT_MAX 64 > > > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > > index 3755a8c2a9de..3a31d34fe709 100644 > > --- a/arch/riscv/kernel/cpufeature.c > > +++ b/arch/riscv/kernel/cpufeature.c > > @@ -182,6 +182,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > > __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), > > __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), > > __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), > > + __RISCV_ISA_EXT_DATA(xventanacondops, RISCV_ISA_EXT_XVENTANACONDOPS), > > }; > > > > const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext); > > -- > > 2.34.1 > > > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv > > I worry about storing vendor extensions in this file. Because vendor > extensions are not standardized, they can only be expected to have the > desired behavior on hardware with the appropriate vendor id. A couple > months ago I sent a patch to address this by handling vector extensions > independently for each vendor [1]. I dropped the patch because it > relied upon Heiko's T-Head vector extension support that he stopped > working on. However, I can revive this patch so you can build off of it. > > This scheme has the added benefit that vendors do not have to worry > about conficting extensions, and the kernel does not have to act as a > key registry for vendors. > > What are your thoughts? > > - Charlie > > [1] https://lore.kernel.org/lkml/20230705-thead_vendor_extensions-v1-2-ad6915349c4d@rivosinc.com/ > I guess I don't need to revive the patch, you could just take the code and update it for xventanacondops. - Charlie _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv