From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B44C2E7849A for ; Mon, 2 Oct 2023 06:27:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=2MchxZSkXyCXGrdH4cp46KWMH6DeIjTVSEWTaXDyJWk=; b=voa84fl7sEtpw0 qeq4vSA7P6jp3LovbXyufmaYeaSHQkFHfr2y8u+1Heh8Jk5BOQEmX1jkUrqP+DYarRpzNzljaCfxt VWC1UsgwRfzHsJnpsf+OcUyydEaWPNxV4qJFn/U0ZfUIeVZNpFWwRqiHk1sOMQNjOzQBVO0IIBvjo gFEx9wZDkM9qaFOac3audx1C5HA+T62vbHqSt5eLkWLrmXGQgBikGNKlE1DU7PY9UpgVqHgtNYih+ UbYhpDLZppuOvfCCYpMdjm5COkkollXP+/yrN3gDUsCSu2zwN8eEfniGJE0j+OPJ0p48c2sGoZuYj 0VmYVOUylAiMTSvjr8yQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qnCOU-00C1bc-1o; Mon, 02 Oct 2023 06:27:02 +0000 Received: from hch by bombadil.infradead.org with local (Exim 4.96 #2 (Red Hat Linux)) id 1qnCOS-00C1bK-1Q; Mon, 02 Oct 2023 06:27:00 +0000 Date: Sun, 1 Oct 2023 23:27:00 -0700 From: Christoph Hellwig To: Anup Patel Cc: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Shuah Khan , Andrew Jones , Mayuresh Chitale , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH 1/7] RISC-V: Detect XVentanaCondOps from ISA string Message-ID: References: <20230919035343.1399389-1-apatel@ventanamicro.com> <20230919035343.1399389-2-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230919035343.1399389-2-apatel@ventanamicro.com> X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, Sep 19, 2023 at 09:23:37AM +0530, Anup Patel wrote: > The Veyron-V1 CPU supports custom conditional arithmetic and > conditional-select/move operations referred to as XVentanaCondOps > extension. In fact, QEMU RISC-V also has support for emulating > XVentanaCondOps extension. > > Let us detect XVentanaCondOps extension from ISA string available > through DT or ACPI. Umm, I though Linux/riscv would never support vendor specific extensions? _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv