* [PATCH v2 05/10] dt-bindings: riscv: Add andestech,cpu-intc to interrupt-controller
@ 2023-10-19 13:59 Yu Chien Peter Lin
2023-10-20 7:00 ` Krzysztof Kozlowski
2023-10-20 9:54 ` Conor Dooley
0 siblings, 2 replies; 4+ messages in thread
From: Yu Chien Peter Lin @ 2023-10-19 13:59 UTC (permalink / raw)
To: conor, robh+dt, krzysztof.kozlowski+dt, paul.walmsley, palmer,
aou, linux-riscv, devicetree, linux-kernel
Cc: prabhakar.mahadev-lad.rj, tim609, dylan, locus84, dminus,
Yu Chien Peter Lin
Add "andestech,cpu-intc" compatible string for Andes INTC which
provides Andes-specific IRQ chip functions.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
---
Changes v1 -> v2:
- New patch
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 97e8441eda1c..5b216e11c69f 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -99,7 +99,9 @@ properties:
const: 1
compatible:
- const: riscv,cpu-intc
+ enum:
+ - riscv,cpu-intc
+ - andestech,cpu-intc
interrupt-controller: true
--
2.34.1
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^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH v2 05/10] dt-bindings: riscv: Add andestech,cpu-intc to interrupt-controller
2023-10-19 13:59 [PATCH v2 05/10] dt-bindings: riscv: Add andestech,cpu-intc to interrupt-controller Yu Chien Peter Lin
@ 2023-10-20 7:00 ` Krzysztof Kozlowski
2023-10-20 8:08 ` Yu-Chien Peter Lin
2023-10-20 9:54 ` Conor Dooley
1 sibling, 1 reply; 4+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-20 7:00 UTC (permalink / raw)
To: Yu Chien Peter Lin, conor, robh+dt, krzysztof.kozlowski+dt,
paul.walmsley, palmer, aou, linux-riscv, devicetree, linux-kernel
Cc: prabhakar.mahadev-lad.rj, tim609, dylan, locus84, dminus
On 19/10/2023 15:59, Yu Chien Peter Lin wrote:
> Add "andestech,cpu-intc" compatible string for Andes INTC which
> provides Andes-specific IRQ chip functions.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> ---
> Changes v1 -> v2:
> - New patch
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 97e8441eda1c..5b216e11c69f 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -99,7 +99,9 @@ properties:
> const: 1
>
> compatible:
> - const: riscv,cpu-intc
> + enum:
> + - riscv,cpu-intc
> + - andestech,cpu-intc
Keep alphabetical order. Do not add stuff to the end of the lists. This
is a generic rule. Everywhere.
Best regards,
Krzysztof
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v2 05/10] dt-bindings: riscv: Add andestech,cpu-intc to interrupt-controller
2023-10-20 7:00 ` Krzysztof Kozlowski
@ 2023-10-20 8:08 ` Yu-Chien Peter Lin
0 siblings, 0 replies; 4+ messages in thread
From: Yu-Chien Peter Lin @ 2023-10-20 8:08 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: conor, robh+dt, krzysztof.kozlowski+dt, paul.walmsley, palmer,
aou, linux-riscv, devicetree, linux-kernel,
prabhakar.mahadev-lad.rj, tim609, dylan, locus84, dminus
On Fri, Oct 20, 2023 at 09:00:03AM +0200, Krzysztof Kozlowski wrote:
> On 19/10/2023 15:59, Yu Chien Peter Lin wrote:
> > Add "andestech,cpu-intc" compatible string for Andes INTC which
> > provides Andes-specific IRQ chip functions.
> >
> > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> > ---
> > Changes v1 -> v2:
> > - New patch
> > ---
> > Documentation/devicetree/bindings/riscv/cpus.yaml | 4 +++-
> > 1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > index 97e8441eda1c..5b216e11c69f 100644
> > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > @@ -99,7 +99,9 @@ properties:
> > const: 1
> >
> > compatible:
> > - const: riscv,cpu-intc
> > + enum:
> > + - riscv,cpu-intc
> > + - andestech,cpu-intc
>
> Keep alphabetical order. Do not add stuff to the end of the lists. This
> is a generic rule. Everywhere.
Hi Krzysztof,
Thansk for pointing this out.
Will fix this in PATCH v3.
Best regards,
Peter Lin
> Best regards,
> Krzysztof
>
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v2 05/10] dt-bindings: riscv: Add andestech,cpu-intc to interrupt-controller
2023-10-19 13:59 [PATCH v2 05/10] dt-bindings: riscv: Add andestech,cpu-intc to interrupt-controller Yu Chien Peter Lin
2023-10-20 7:00 ` Krzysztof Kozlowski
@ 2023-10-20 9:54 ` Conor Dooley
1 sibling, 0 replies; 4+ messages in thread
From: Conor Dooley @ 2023-10-20 9:54 UTC (permalink / raw)
To: Yu Chien Peter Lin
Cc: robh+dt, krzysztof.kozlowski+dt, paul.walmsley, palmer, aou,
linux-riscv, devicetree, linux-kernel, prabhakar.mahadev-lad.rj,
tim609, dylan, locus84, dminus
[-- Attachment #1.1: Type: text/plain, Size: 1301 bytes --]
Yo,
On Thu, Oct 19, 2023 at 09:59:05PM +0800, Yu Chien Peter Lin wrote:
> Add "andestech,cpu-intc" compatible string for Andes INTC which
> provides Andes-specific IRQ chip functions.
You need to provide some information as to what differentiates your intc
from the regular one, not mention linux driver specifics.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> ---
> Changes v1 -> v2:
> - New patch
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 97e8441eda1c..5b216e11c69f 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -99,7 +99,9 @@ properties:
> const: 1
>
> compatible:
> - const: riscv,cpu-intc
> + enum:
> + - riscv,cpu-intc
> + - andestech,cpu-intc
Should the andestech intc not fall back to the generic intc compatible?
The generic one appears to implement a compatible subset of the features
that yours does.
Cheers,
Conor.
>
> interrupt-controller: true
>
> --
> 2.34.1
>
>
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2023-10-19 13:59 [PATCH v2 05/10] dt-bindings: riscv: Add andestech,cpu-intc to interrupt-controller Yu Chien Peter Lin
2023-10-20 7:00 ` Krzysztof Kozlowski
2023-10-20 8:08 ` Yu-Chien Peter Lin
2023-10-20 9:54 ` Conor Dooley
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