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Wed, 25 Oct 2023 13:37:24 -0700 (PDT) Date: Wed, 25 Oct 2023 13:37:21 -0700 From: Charlie Jenkins To: "Wang, Xiao W" Subject: Re: [PATCH v7 2/4] riscv: Checksum header Message-ID: References: <20230919-optimize_checksum-v7-0-06c7d0ddd5d6@rivosinc.com> <20230919-optimize_checksum-v7-2-06c7d0ddd5d6@rivosinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231025_133728_363157_54890E62 X-CRM114-Status: GOOD ( 34.64 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "linux-arch@vger.kernel.org" , Albert Ou , Arnd Bergmann , "linux-kernel@vger.kernel.org" , Conor Dooley , David Laight , Palmer Dabbelt , Paul Walmsley , "linux-riscv@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, Oct 25, 2023 at 06:50:05AM +0000, Wang, Xiao W wrote: > Hi Charlie, > > > -----Original Message----- > > From: linux-riscv On Behalf Of > > Charlie Jenkins > > Sent: Wednesday, September 20, 2023 2:45 AM > > To: Charlie Jenkins ; Palmer Dabbelt > > ; Conor Dooley ; Samuel Holland > > ; David Laight ; > > linux-riscv@lists.infradead.org; linux-kernel@vger.kernel.org; linux- > > arch@vger.kernel.org > > Cc: Paul Walmsley ; Albert Ou > > ; Arnd Bergmann > > Subject: [PATCH v7 2/4] riscv: Checksum header > > > > Provide checksum algorithms that have been designed to leverage riscv > > instructions such as rotate. In 64-bit, can take advantage of the larger > > register to avoid some overflow checking. > > > > Signed-off-by: Charlie Jenkins > > --- > > arch/riscv/include/asm/checksum.h | 79 > > +++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 79 insertions(+) > > > > diff --git a/arch/riscv/include/asm/checksum.h > > b/arch/riscv/include/asm/checksum.h > > new file mode 100644 > > index 000000000000..dc0dd89f2a13 > > --- /dev/null > > +++ b/arch/riscv/include/asm/checksum.h > > @@ -0,0 +1,79 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +/* > > + * IP checksum routines > > + * > > + * Copyright (C) 2023 Rivos Inc. > > + */ > > +#ifndef __ASM_RISCV_CHECKSUM_H > > +#define __ASM_RISCV_CHECKSUM_H > > + > > +#include > > +#include > > + > > +#define ip_fast_csum ip_fast_csum > > + > > +#include > > + > > +/* > > + * Quickly compute an IP checksum with the assumption that IPv4 headers > > will > > + * always be in multiples of 32-bits, and have an ihl of at least 5. > > + * @ihl is the number of 32 bit segments and must be greater than or equal > > to 5. > > + * @iph is assumed to be word aligned. > > Not sure if the assumption is always true. It looks the implementation in "lib/checksum.c" doesn't take this assumption. > The ip header can comes after a 14-Byte ether header, which may start from a word-aligned or DMA friendly address. While lib/checksum.c does not make this assumption, other architectures (x86, ARM, powerpc, mips, arc) do make this assumption. Architectures seem to only align the header on a word boundary in do_csum. I worry that the benefit of aligning iph in this "fast" csum function would disproportionately impact hardware that has fast misaligned accesses. - Charlie > > > + */ > > +static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl) > > +{ > > + unsigned long csum = 0; > > + int pos = 0; > > + > > + do { > > + csum += ((const unsigned int *)iph)[pos]; > > + if (IS_ENABLED(CONFIG_32BIT)) > > + csum += csum < ((const unsigned int *)iph)[pos]; > > + } while (++pos < ihl); > > + > > + /* > > + * ZBB only saves three instructions on 32-bit and five on 64-bit so not > > + * worth checking if supported without Alternatives. > > + */ > > + if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && > > + IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) { > > + unsigned long fold_temp; > > + > > + asm_volatile_goto(ALTERNATIVE("j %l[no_zbb]", "nop", 0, > > + RISCV_ISA_EXT_ZBB, 1) > > + : > > + : > > + : > > + : no_zbb); > > + > > + if (IS_ENABLED(CONFIG_32BIT)) { > > + asm(".option push \n\ > > + .option arch,+zbb \n\ > > + not %[fold_temp], %[csum] > > \n\ > > + rori %[csum], %[csum], 16 \n\ > > + sub %[csum], %[fold_temp], %[csum] > > \n\ > > + .option pop" > > + : [csum] "+r" (csum), [fold_temp] "=&r" (fold_temp)); > > + } else { > > + asm(".option push \n\ > > + .option arch,+zbb \n\ > > + rori %[fold_temp], %[csum], 32 \n\ > > + add %[csum], %[fold_temp], %[csum] > > \n\ > > + srli %[csum], %[csum], 32 \n\ > > + not %[fold_temp], %[csum] > > \n\ > > + roriw %[csum], %[csum], 16 \n\ > > + subw %[csum], %[fold_temp], %[csum] > > \n\ > > + .option pop" > > + : [csum] "+r" (csum), [fold_temp] "=&r" (fold_temp)); > > + } > > + return csum >> 16; > > + } > > +no_zbb: > > +#ifndef CONFIG_32BIT > > + csum += (csum >> 32) | (csum << 32); > > Just like patch 3/4 does, we can call ror64(csum, 32). > > BRs, > Xiao > > > + csum >>= 32; > > +#endif > > + return csum_fold((__force __wsum)csum); > > +} > > + > > +#endif // __ASM_RISCV_CHECKSUM_H > > > > -- > > 2.42.0 > > > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv