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Tue, 31 Oct 2023 15:53:30 -0700 (PDT) Date: Tue, 31 Oct 2023 15:53:28 -0700 From: Charlie Jenkins To: "Wang, Xiao W" Cc: Palmer Dabbelt , Conor Dooley , Samuel Holland , David Laight , Evan Green , "linux-riscv@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-arch@vger.kernel.org" , Paul Walmsley , Albert Ou , Arnd Bergmann , Conor Dooley Subject: Re: [PATCH v8 3/5] riscv: Checksum header Message-ID: References: <20231027-optimize_checksum-v8-0-feb7101d128d@rivosinc.com> <20231027-optimize_checksum-v8-3-feb7101d128d@rivosinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231031_155333_272124_9AB52A4E X-CRM114-Status: GOOD ( 35.14 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, Oct 31, 2023 at 09:11:07AM +0000, Wang, Xiao W wrote: > > > > -----Original Message----- > > From: Charlie Jenkins > > Sent: Saturday, October 28, 2023 6:44 AM > > To: Charlie Jenkins ; Palmer Dabbelt > > ; Conor Dooley ; Samuel Holland > > ; David Laight ; > > Wang, Xiao W ; Evan Green ; > > linux-riscv@lists.infradead.org; linux-kernel@vger.kernel.org; linux- > > arch@vger.kernel.org > > Cc: Paul Walmsley ; Albert Ou > > ; Arnd Bergmann ; Conor Dooley > > > > Subject: [PATCH v8 3/5] riscv: Checksum header > > > > Provide checksum algorithms that have been designed to leverage riscv > > instructions such as rotate. In 64-bit, can take advantage of the larger > > register to avoid some overflow checking. > > > > Signed-off-by: Charlie Jenkins > > Acked-by: Conor Dooley > > --- > > arch/riscv/include/asm/checksum.h | 92 > > +++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 92 insertions(+) > > > > diff --git a/arch/riscv/include/asm/checksum.h > > b/arch/riscv/include/asm/checksum.h > > new file mode 100644 > > index 000000000000..9fd4b1b80641 > > --- /dev/null > > +++ b/arch/riscv/include/asm/checksum.h > > @@ -0,0 +1,92 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +/* > > + * IP checksum routines > > The checksum helpers' usage may not be limited to IP protocol. > Will remove IP from the wording. > > + * > > + * Copyright (C) 2023 Rivos Inc. > > + */ > > +#ifndef __ASM_RISCV_CHECKSUM_H > > +#define __ASM_RISCV_CHECKSUM_H > > + > > +#include > > +#include > > + > > +#define ip_fast_csum ip_fast_csum > > + > > +extern unsigned int do_csum(const unsigned char *buff, int len); > > +#define do_csum do_csum > > + > > +/* Default version is sufficient for 32 bit */ > > +#ifdef CONFIG_64BIT > > +#define _HAVE_ARCH_IPV6_CSUM > > +__sum16 csum_ipv6_magic(const struct in6_addr *saddr, > > + const struct in6_addr *daddr, > > + __u32 len, __u8 proto, __wsum sum); > > +#endif > > The do_csum and csum_ipv6_magic helpers are implemented in patch 4/5, so the > declarations should be moved there. Otherwise, build would fail at this patch. > Oops, that snuck into this patch somehow. > > + > > +/* Define riscv versions of functions before importing asm- > > generic/checksum.h */ > > +#include > > + > > +/* > > + * Quickly compute an IP checksum with the assumption that IPv4 headers > > will > > + * always be in multiples of 32-bits, and have an ihl of at least 5. > > + * @ihl is the number of 32 bit segments and must be greater than or equal > > to 5. > > + * @iph is assumed to be word aligned given that NET_IP_ALIGN is set to 2 on > > + * riscv, defining IP headers to be aligned. > > + */ > > +static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl) > > +{ > > + unsigned long csum = 0; > > + int pos = 0; > > + > > + do { > > + csum += ((const unsigned int *)iph)[pos]; > > + if (IS_ENABLED(CONFIG_32BIT)) > > + csum += csum < ((const unsigned int *)iph)[pos]; > > + } while (++pos < ihl); > > + > > + /* > > + * ZBB only saves three instructions on 32-bit and five on 64-bit so not > > + * worth checking if supported without Alternatives. > > + */ > > + if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && > > + IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) { > > + unsigned long fold_temp; > > + > > + asm_volatile_goto(ALTERNATIVE("j %l[no_zbb]", "nop", 0, > > + RISCV_ISA_EXT_ZBB, 1) > > + : > > + : > > + : > > + : no_zbb); > > + > > + if (IS_ENABLED(CONFIG_32BIT)) { > > + asm(".option push \n\ > > + .option arch,+zbb \n\ > > + not %[fold_temp], %[csum] > > \n\ > > + rori %[csum], %[csum], 16 \n\ > > + sub %[csum], %[fold_temp], %[csum] > > \n\ > > + .option pop" > > + : [csum] "+r" (csum), [fold_temp] "=&r" (fold_temp)); > > + } else { > > + asm(".option push \n\ > > + .option arch,+zbb \n\ > > + rori %[fold_temp], %[csum], 32 \n\ > > + add %[csum], %[fold_temp], %[csum] > > \n\ > > + srli %[csum], %[csum], 32 \n\ > > + not %[fold_temp], %[csum] > > \n\ > > + roriw %[csum], %[csum], 16 \n\ > > + subw %[csum], %[fold_temp], %[csum] > > \n\ > > + .option pop" > > + : [csum] "+r" (csum), [fold_temp] "=&r" (fold_temp)); > > + } > > + return csum >> 16; > > + } > > +no_zbb: > > +#ifndef CONFIG_32BIT > > + csum += (csum >> 32) | (csum << 32); > > Just like the next patch does, we can call ror64(csum, 32). I meant to change this last time, thank you for pointing it out again. - Charlie > > BRs, > Xiao > > > + csum >>= 32; > > +#endif > > + return csum_fold((__force __wsum)csum); > > +} > > + > > +#endif /* __ASM_RISCV_CHECKSUM_H */ > > > > -- > > 2.42.0 > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv