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Mon, 04 Dec 2023 11:15:30 -0800 (PST) Date: Mon, 4 Dec 2023 11:15:28 -0800 From: Charlie Jenkins To: Jisheng Zhang Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 1/2] riscv: introduce RISCV_EFFICIENT_UNALIGNED_ACCESS Message-ID: References: <20231203135753.1575-1-jszhang@kernel.org> <20231203135753.1575-2-jszhang@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20231203135753.1575-2-jszhang@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231204_111532_680725_6C39E7BB X-CRM114-Status: GOOD ( 26.00 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Sun, Dec 03, 2023 at 09:57:52PM +0800, Jisheng Zhang wrote: > Some riscv implementations such as T-HEAD's C906, C908, C910 and C920 > support efficient unaligned access, for performance reason we want > to enable HAVE_EFFICIENT_UNALIGNED_ACCESS on these platforms. To > avoid performance regressions on other non efficient unaligned access > platforms, HAVE_EFFICIENT_UNALIGNED_ACCESS can't be globally selected. > > To solve this problem, runtime code patching based on the detected > speed is a good solution. But that's not easy, it involves lots of > work to modify vairous subsystems such as net, mm, lib and so on. > This can be done step by step. > > So let's take an easier solution: add support to efficient unaligned > access and hide the support under NONPORTABLE. > > Now let's introduce RISCV_EFFICIENT_UNALIGNED_ACCESS which depends on > NONPORTABLE, if users know during config time that the kernel will be > only run on those efficient unaligned access hw platforms, they can > enable it. Obviously, generic unified kernel Image shouldn't enable it. > > Signed-off-by: Jisheng Zhang > --- > arch/riscv/Kconfig | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index 7f8aa25457ba..0a76209e9b02 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -654,6 +654,18 @@ config RISCV_MISALIGNED > load/store for both kernel and userspace. When disable, misaligned > accesses will generate SIGBUS in userspace and panic in kernel. > > +config RISCV_EFFICIENT_UNALIGNED_ACCESS There already exists hwprobe for this purpose. If kernel code wants to leverage the efficient unaligned accesses of hardware, it can use static keys. I have a patch that will set this static key if the hardware was detected to have fast unaligned accesses: https://lore.kernel.org/linux-riscv/20231117-optimize_checksum-v11-2-7d9d954fe361@rivosinc.com/ - Charlie > + bool "Use unaligned access for some functions" > + depends on NONPORTABLE > + select HAVE_EFFICIENT_UNALIGNED_ACCESS > + default n > + help > + Say Y here if you want the kernel only run on hardware platforms which > + support efficient unaligned access, then unaligned access will be used > + in some functions for optimized performance. > + > + If unsure what to do here, say N. > + > endmenu # "Platform type" > > menu "Kernel features" > -- > 2.42.0 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv