[PATCH] riscv: fixup endian issues in module code

[PATCH] riscv: fixup endian issues in module code

[Ben Dooks]

There is a couple of places in the module.c file where it
is using u16 where it meant __le16. Change this and fix
the following sparse warnings:

arch/riscv/kernel/module.c:68:25: warning: cast to restricted __le16
arch/riscv/kernel/module.c:68:55: warning: cast to restricted __le16
arch/riscv/kernel/module.c:73:19: warning: incorrect type in assignment (different base types)
arch/riscv/kernel/module.c:73:19:    expected unsigned short [usertype]
arch/riscv/kernel/module.c:73:19:    got restricted __le16 [usertype]
arch/riscv/kernel/module.c:74:19: warning: incorrect type in assignment (different base types)
arch/riscv/kernel/module.c:74:19:    expected unsigned short [usertype]
arch/riscv/kernel/module.c:74:19:    got restricted __le16 [usertype]
arch/riscv/kernel/module.c:81:20: warning: cast to restricted __le16
arch/riscv/kernel/module.c:86:17: warning: incorrect type in assignment (different base types)
arch/riscv/kernel/module.c:86:17:    expected unsigned short [usertype]
arch/riscv/kernel/module.c:86:17:    got restricted __le16 [usertype]

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
 arch/riscv/kernel/module.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c
index b5109a3889c9..82f9266ae434 100644
--- a/arch/riscv/kernel/module.c
+++ b/arch/riscv/kernel/module.c
@@ -64,7 +64,7 @@ static bool riscv_insn_valid_32bit_offset(ptrdiff_t val)
 
 static int riscv_insn_rmw(void *location, u32 keep, u32 set)
 {
-	u16 *parcel = location;
+	__le16 *parcel = location;
 	u32 insn = (u32)le16_to_cpu(parcel[0]) | (u32)le16_to_cpu(parcel[1]) << 16;
 
 	insn &= keep;
@@ -77,7 +77,7 @@ static int riscv_insn_rmw(void *location, u32 keep, u32 set)
 
 static int riscv_insn_rvc_rmw(void *location, u16 keep, u16 set)
 {
-	u16 *parcel = location;
+	__le16  *parcel = location;
 	u16 insn = le16_to_cpu(*parcel);
 
 	insn &= keep;
-- 
2.37.2.352.g3c44437643


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Re: [PATCH] riscv: fixup endian issues in module code

[Charlie Jenkins]

On Wed, Nov 22, 2023 at 10:45:47AM +0000, Ben Dooks wrote:
> There is a couple of places in the module.c file where it
> is using u16 where it meant __le16. Change this and fix
> the following sparse warnings:
> 
> arch/riscv/kernel/module.c:68:25: warning: cast to restricted __le16
> arch/riscv/kernel/module.c:68:55: warning: cast to restricted __le16
> arch/riscv/kernel/module.c:73:19: warning: incorrect type in assignment (different base types)
> arch/riscv/kernel/module.c:73:19:    expected unsigned short [usertype]
> arch/riscv/kernel/module.c:73:19:    got restricted __le16 [usertype]
> arch/riscv/kernel/module.c:74:19: warning: incorrect type in assignment (different base types)
> arch/riscv/kernel/module.c:74:19:    expected unsigned short [usertype]
> arch/riscv/kernel/module.c:74:19:    got restricted __le16 [usertype]
> arch/riscv/kernel/module.c:81:20: warning: cast to restricted __le16
> arch/riscv/kernel/module.c:86:17: warning: incorrect type in assignment (different base types)
> arch/riscv/kernel/module.c:86:17:    expected unsigned short [usertype]
> arch/riscv/kernel/module.c:86:17:    got restricted __le16 [usertype]
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> ---
>  arch/riscv/kernel/module.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c
> index b5109a3889c9..82f9266ae434 100644
> --- a/arch/riscv/kernel/module.c
> +++ b/arch/riscv/kernel/module.c
> @@ -64,7 +64,7 @@ static bool riscv_insn_valid_32bit_offset(ptrdiff_t val)
>  
>  static int riscv_insn_rmw(void *location, u32 keep, u32 set)
>  {
> -	u16 *parcel = location;
> +	__le16 *parcel = location;
>  	u32 insn = (u32)le16_to_cpu(parcel[0]) | (u32)le16_to_cpu(parcel[1]) << 16;
>  
>  	insn &= keep;
> @@ -77,7 +77,7 @@ static int riscv_insn_rmw(void *location, u32 keep, u32 set)
>  
>  static int riscv_insn_rvc_rmw(void *location, u16 keep, u16 set)
>  {
> -	u16 *parcel = location;
> +	__le16  *parcel = location;
>  	u16 insn = le16_to_cpu(*parcel);
>  
>  	insn &= keep;
> -- 
> 2.37.2.352.g3c44437643
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

We had the same idea :). I sent out a patch with the same changes a
couple days before this [1]. I did some shuffling of my series and the
patch ended up in [2] which will hopefully end up in an rc soon.

[1] https://lore.kernel.org/lkml/20231117-module_fixup-v1-2-62bb777f6825@rivosinc.com/
[2] https://lore.kernel.org/linux-riscv/20231127-module_linking_freeing-v4-2-a2ca1d7027d0@rivosinc.com/


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