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Mon, 11 Dec 2023 11:58:16 -0800 (PST) Received: from ghost ([12.44.203.122]) by smtp.gmail.com with ESMTPSA id f8-20020a170902ce8800b001cfc46baa40sm7051945plg.158.2023.12.11.11.58.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Dec 2023 11:58:16 -0800 (PST) Date: Mon, 11 Dec 2023 11:58:13 -0800 From: Charlie Jenkins To: =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jonathan Corbet , Conor Dooley , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Subject: Re: [PATCH v2 1/2] riscv: Include riscv_set_icache_flush_ctx prctl Message-ID: References: <20231130-fencei-v2-0-2cb623ab1b1f@rivosinc.com> <20231130-fencei-v2-1-2cb623ab1b1f@rivosinc.com> <42e0c9d4-318e-4c84-bdfb-fd364bea02d5@rivosinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <42e0c9d4-318e-4c84-bdfb-fd364bea02d5@rivosinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231211_115819_915745_608DA238 X-CRM114-Status: GOOD ( 34.48 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Dec 11, 2023 at 10:12:42AM +0100, Cl=E9ment L=E9ger wrote: > = > = > On 01/12/2023 08:21, Charlie Jenkins wrote: > > Support new prctl with key PR_RISCV_SET_ICACHE_FLUSH_CTX to enable > > optimization of cross modifying code. This prctl enables userspace code > > to use icache flushing instructions such as fence.i with the guarantee > > that the icache will continue to be clean after thread migration. > > = > > Signed-off-by: Charlie Jenkins > > --- > > arch/riscv/include/asm/mmu.h | 2 ++ > > arch/riscv/include/asm/processor.h | 6 ++++++ > > arch/riscv/mm/cacheflush.c | 37 ++++++++++++++++++++++++++++++= +++++++ > > arch/riscv/mm/context.c | 8 +++++--- > > include/uapi/linux/prctl.h | 3 +++ > > kernel/sys.c | 6 ++++++ > > 6 files changed, 59 insertions(+), 3 deletions(-) > > = > > diff --git a/arch/riscv/include/asm/mmu.h b/arch/riscv/include/asm/mmu.h > > index 355504b37f8e..60be458e94da 100644 > > --- a/arch/riscv/include/asm/mmu.h > > +++ b/arch/riscv/include/asm/mmu.h > > @@ -19,6 +19,8 @@ typedef struct { > > #ifdef CONFIG_SMP > > /* A local icache flush is needed before user execution can resume. */ > > cpumask_t icache_stale_mask; > > + /* Force local icache flush on all migrations. */ > > + bool force_icache_flush; > > #endif > > #ifdef CONFIG_BINFMT_ELF_FDPIC > > unsigned long exec_fdpic_loadmap; > > diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/as= m/processor.h > > index f19f861cda54..7eda6c75e0f2 100644 > > --- a/arch/riscv/include/asm/processor.h > > +++ b/arch/riscv/include/asm/processor.h > > @@ -84,6 +84,9 @@ struct thread_struct { > > unsigned long vstate_ctrl; > > struct __riscv_v_ext_state vstate; > > unsigned long align_ctl; > > +#ifdef CONFIG_SMP > > + bool force_icache_flush; > > +#endif > > }; > > = > > /* Whitelist the fstate from the task_struct for hardened usercopy */ > > @@ -145,6 +148,9 @@ extern int set_unalign_ctl(struct task_struct *tsk,= unsigned int val); > > #define GET_UNALIGN_CTL(tsk, addr) get_unalign_ctl((tsk), (addr)) > > #define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val)) > > = > > +#define RISCV_SET_ICACHE_FLUSH_CTX(arg1, arg2) riscv_set_icache_flush_= ctx(arg1, arg2) > > +extern int riscv_set_icache_flush_ctx(unsigned long ctx, unsigned long= per_thread); > > + > > #endif /* __ASSEMBLY__ */ > > = > > #endif /* _ASM_RISCV_PROCESSOR_H */ > > diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c > > index 55a34f2020a8..3b2bf8256a10 100644 > > --- a/arch/riscv/mm/cacheflush.c > > +++ b/arch/riscv/mm/cacheflush.c > > @@ -5,6 +5,7 @@ > > = > > #include > > #include > > +#include > > #include > > #include > > = > > @@ -152,3 +153,39 @@ void __init riscv_init_cbo_blocksizes(void) > > if (cboz_block_size) > > riscv_cboz_block_size =3D cboz_block_size; > > } > > + > > +/** > > + * riscv_set_icache_flush_ctx() - Enable userspace to emit icache flus= hing instructions. > > + * @ctx: Sets the type of context > > + * - PR_RISCV_CTX_SW_FENCEI: Allow fence.i in userspace. Another fenc= e.i will > > + * emitted on thread/process migration. > > + * @per_thread: When set to 0, will use the default behavior of settin= g the > > + * icache flush context per process. When set to 1, will use a per th= read > > + * context. > > + * > > + * When in per-process context, there may be multiple threads using th= e same mm. > > + * Therefore, the icache can never be assumed clean when. Multiple thr= eads in > > + * the process may modify instructions in the mm concurrently. > > + * > > + * In per-thread context, it can be assumed that all modifications to > > + * instructions in memory will be performed by this thread. When the t= hread is > > + * migrated the icache will be flushed. > > + * > > + */ > > +int riscv_set_icache_flush_ctx(unsigned long ctx, unsigned long per_th= read) > > +{ > > +#ifdef CONFIG_SMP > > + switch (ctx) { > > + case PR_RISCV_CTX_SW_FENCEI: > > + if (per_thread) > > + current->thread.force_icache_flush =3D true; > > + else > > + current->mm->context.force_icache_flush =3D true; > > + break; > > + > > + default: > > + break; > > + } > > +#endif > > + return 0; > > +} > > diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c > > index 217fd4de6134..a394b146e78a 100644 > > --- a/arch/riscv/mm/context.c > > +++ b/arch/riscv/mm/context.c > > @@ -297,12 +297,14 @@ static inline void set_mm(struct mm_struct *prev, > > * > > * The "cpu" argument must be the current local CPU number. > > */ > > -static inline void flush_icache_deferred(struct mm_struct *mm, unsigne= d int cpu) > > +static inline void flush_icache_deferred(struct mm_struct *mm, unsigne= d int cpu, > > + struct task_struct *task) > > { > > #ifdef CONFIG_SMP > > cpumask_t *mask =3D &mm->context.icache_stale_mask; > > = > > - if (cpumask_test_cpu(cpu, mask)) { > > + if (cpumask_test_cpu(cpu, mask) || mm->context.force_icache_flush || > > + mm->context.force_icache_flush) { > = > Hey Charlie, > = > Looks like you duplicated "||=A0mm->context.force_icache_flush" here. > = Whoops, will send out a fix for that. - Charlie > Cl=E9ment > = > > cpumask_clear_cpu(cpu, mask); > > /* > > * Ensure the remote hart's writes are visible to this hart. > > @@ -332,5 +334,5 @@ void switch_mm(struct mm_struct *prev, struct mm_st= ruct *next, > > = > > set_mm(prev, next, cpu); > > = > > - flush_icache_deferred(next, cpu); > > + flush_icache_deferred(next, cpu, task); > > } > > diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h > > index 370ed14b1ae0..472801ea78cc 100644 > > --- a/include/uapi/linux/prctl.h > > +++ b/include/uapi/linux/prctl.h > > @@ -306,4 +306,7 @@ struct prctl_mm_map { > > # define PR_RISCV_V_VSTATE_CTRL_NEXT_MASK 0xc > > # define PR_RISCV_V_VSTATE_CTRL_MASK 0x1f > > = > > +#define PR_RISCV_SET_ICACHE_FLUSH_CTX 71 > > +# define PR_RISCV_CTX_SW_FENCEI 0 > > + > > #endif /* _LINUX_PRCTL_H */ > > diff --git a/kernel/sys.c b/kernel/sys.c > > index 420d9cb9cc8e..e806a8a67c36 100644 > > --- a/kernel/sys.c > > +++ b/kernel/sys.c > > @@ -146,6 +146,9 @@ > > #ifndef RISCV_V_GET_CONTROL > > # define RISCV_V_GET_CONTROL() (-EINVAL) > > #endif > > +#ifndef RISCV_SET_ICACHE_FLUSH_CTX > > +# define RISCV_SET_ICACHE_FLUSH_CTX(a, b) (-EINVAL) > > +#endif > > = > > /* > > * this is where the system-wide overflow UID and GID are defined, for > > @@ -2739,6 +2742,9 @@ SYSCALL_DEFINE5(prctl, int, option, unsigned long= , arg2, unsigned long, arg3, > > case PR_RISCV_V_GET_CONTROL: > > error =3D RISCV_V_GET_CONTROL(); > > break; > > + case PR_RISCV_SET_ICACHE_FLUSH_CTX: > > + error =3D RISCV_SET_ICACHE_FLUSH_CTX(arg2, arg3); > > + break; > > default: > > error =3D -EINVAL; > > break; > > = _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv