Re: [v8, 01/10] riscv: Add support for kernel mode vector

[Charlie Jenkins <charlie@rivosinc.com>]

On Wed, Dec 27, 2023 at 05:18:10PM +0800, Andy Chiu wrote:
> On Wed, Dec 27, 2023 at 1:30 PM Charlie Jenkins <charlie@rivosinc.com> wrote:
> >
> > On Wed, Dec 27, 2023 at 10:46:58AM +0800, Andy Chiu wrote:
> > > On Wed, Dec 27, 2023 at 9:36 AM Charlie Jenkins <charlie@rivosinc.com> wrote:
> > > >
> > > > On Sat, Dec 23, 2023 at 04:29:05AM +0000, Andy Chiu wrote:
> > > > > From: Greentime Hu <greentime.hu@sifive.com>
> > > > >
> > > > > Add kernel_vector_begin() and kernel_vector_end() function declarations
> > > > > and corresponding definitions in kernel_mode_vector.c
> > > > >
> > > > > These are needed to wrap uses of vector in kernel mode.
> > > > >
> > > > > Co-developed-by: Vincent Chen <vincent.chen@sifive.com>
> > > > > Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
> > > > > Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> > > > > Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> > > > > ---
> > > > > Changelog v8:
> > > > >  - Refactor unnecessary whitespace change (Eric)
> > > > > Changelog v7:
> > > > >  - fix build fail for allmodconfig
> > > > > Changelog v6:
> > > > >  - Use 8 bits to track non-preemptible vector context to provide better
> > > > >    WARN coverage.
> > > > > Changelog v4:
> > > > >  - Use kernel_v_flags and helpers to track vector context.
> > > > > Changelog v3:
> > > > >  - Reorder patch 1 to patch 3 to make use of
> > > > >    {get,put}_cpu_vector_context later.
> > > > >  - Export {get,put}_cpu_vector_context.
> > > > >  - Save V context after disabling preemption. (Guo)
> > > > >  - Fix a build fail. (Conor)
> > > > >  - Remove irqs_disabled() check as it is not needed, fix styling. (Björn)
> > > > > Changelog v2:
> > > > >  - 's/kernel_rvv/kernel_vector' and return void in kernel_vector_begin
> > > > >    (Conor)
> > > > >  - export may_use_simd to include/asm/simd.h
> > > > > ---
> > > > >  arch/riscv/include/asm/processor.h     | 17 ++++-
> > > > >  arch/riscv/include/asm/simd.h          | 44 ++++++++++++
> > > > >  arch/riscv/include/asm/vector.h        | 21 ++++++
> > > > >  arch/riscv/kernel/Makefile             |  1 +
> > > > >  arch/riscv/kernel/kernel_mode_vector.c | 95 ++++++++++++++++++++++++++
> > > > >  arch/riscv/kernel/process.c            |  1 +
> > > > >  6 files changed, 178 insertions(+), 1 deletion(-)
> > > > >  create mode 100644 arch/riscv/include/asm/simd.h
> > > > >  create mode 100644 arch/riscv/kernel/kernel_mode_vector.c
> > > > >
> > > > > diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
> > > > > index f19f861cda54..15781e2232e0 100644
> > > > > --- a/arch/riscv/include/asm/processor.h
> > > > > +++ b/arch/riscv/include/asm/processor.h
> > > > > @@ -73,6 +73,20 @@
> > > > >  struct task_struct;
> > > > >  struct pt_regs;
> > > > >
> > > > > +/*
> > > > > + * We use a flag to track in-kernel Vector context. Currently the flag has the
> > > > > + * following meaning:
> > > > > + *
> > > > > + *  - bit 0-7 indicates whether the in-kernel Vector context is active. The
> > > > > + *    activation of this state disables the preemption. On a non-RT kernel, it
> > > > > + *    also disable bh. Currently only 0 and 1 are valid value for this field.
> > > > > + *    Other values are reserved for future uses.
> > > > > + */
> > > > > +
> > > > > +#define RISCV_KERNEL_MODE_V_MASK     0xff
> > > > > +
> > > > > +#define RISCV_KERNEL_MODE_V  0x1
> > > > > +
> > > > >  /* CPU-specific state of a task */
> > > > >  struct thread_struct {
> > > > >       /* Callee-saved registers */
> > > > > @@ -81,7 +95,8 @@ struct thread_struct {
> > > > >       unsigned long s[12];    /* s[0]: frame pointer */
> > > > >       struct __riscv_d_ext_state fstate;
> > > > >       unsigned long bad_cause;
> > > > > -     unsigned long vstate_ctrl;
> > > > > +     u32 riscv_v_flags;
> > > > > +     u32 vstate_ctrl;
> > > > >       struct __riscv_v_ext_state vstate;
> > > > >       unsigned long align_ctl;
> > > > >  };
> > > > > diff --git a/arch/riscv/include/asm/simd.h b/arch/riscv/include/asm/simd.h
> > > > > new file mode 100644
> > > > > index 000000000000..3b603e47c5d8
> > > > > --- /dev/null
> > > > > +++ b/arch/riscv/include/asm/simd.h
> > > > > @@ -0,0 +1,44 @@
> > > > > +/* SPDX-License-Identifier: GPL-2.0-only */
> > > > > +/*
> > > > > + * Copyright (C) 2017 Linaro Ltd. <ard.biesheuvel@linaro.org>
> > > > > + * Copyright (C) 2023 SiFive
> > > > > + */
> > > > > +
> > > > > +#ifndef __ASM_SIMD_H
> > > > > +#define __ASM_SIMD_H
> > > > > +
> > > > > +#include <linux/compiler.h>
> > > > > +#include <linux/irqflags.h>
> > > > > +#include <linux/percpu.h>
> > > > > +#include <linux/preempt.h>
> > > > > +#include <linux/types.h>
> > > > > +
> > > > > +#include <asm/vector.h>
> > > > > +
> > > > > +#ifdef CONFIG_RISCV_ISA_V
> > > > > +/*
> > > > > + * may_use_simd - whether it is allowable at this time to issue vector
> > > > > + *                instructions or access the vector register file
> > > > > + *
> > > > > + * Callers must not assume that the result remains true beyond the next
> > > > > + * preempt_enable() or return from softirq context.
> > > > > + */
> > > > > +static __must_check inline bool may_use_simd(void)
> > > > > +{
> > > > > +     /*
> > > > > +      * RISCV_KERNEL_MODE_V is only set while preemption is disabled,
> > > > > +      * and is clear whenever preemption is enabled.
> > > > > +      */
> > > > > +     return !in_hardirq() && !in_nmi() && !(riscv_v_ctx_cnt() & RISCV_KERNEL_MODE_V_MASK);
> > > > > +}
> > > > > +
> > > > > +#else /* ! CONFIG_RISCV_ISA_V */
> > > > > +
> > > > > +static __must_check inline bool may_use_simd(void)
> > > > > +{
> > > > > +     return false;
> > > > > +}
> > > > > +
> > > > > +#endif /* ! CONFIG_RISCV_ISA_V */
> > > > > +
> > > > > +#endif
> > > > > diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
> > > > > index 87aaef656257..6254830c0668 100644
> > > > > --- a/arch/riscv/include/asm/vector.h
> > > > > +++ b/arch/riscv/include/asm/vector.h
> > > > > @@ -22,6 +22,27 @@
> > > > >  extern unsigned long riscv_v_vsize;
> > > > >  int riscv_v_setup_vsize(void);
> > > > >  bool riscv_v_first_use_handler(struct pt_regs *regs);
> > > > > +void kernel_vector_begin(void);
> > > > > +void kernel_vector_end(void);
> > > > > +void get_cpu_vector_context(void);
> > > > > +void put_cpu_vector_context(void);
> > > > > +
> > > > > +static inline void riscv_v_ctx_cnt_add(u32 offset)
> > > > > +{
> > > > > +     current->thread.riscv_v_flags += offset;
> > > > > +     barrier();
> > > > > +}
> > > > > +
> > > > > +static inline void riscv_v_ctx_cnt_sub(u32 offset)
> > > > > +{
> > > > > +     barrier();
> > > > > +     current->thread.riscv_v_flags -= offset;
> > > > > +}
> > > > > +
> > > > > +static inline u32 riscv_v_ctx_cnt(void)
> > > > > +{
> > > > > +     return READ_ONCE(current->thread.riscv_v_flags);
> > > > > +}
> > > > >
> > > > >  static __always_inline bool has_vector(void)
> > > > >  {
> > > > > diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
> > > > > index fee22a3d1b53..8c58595696b3 100644
> > > > > --- a/arch/riscv/kernel/Makefile
> > > > > +++ b/arch/riscv/kernel/Makefile
> > > > > @@ -63,6 +63,7 @@ obj-$(CONFIG_MMU) += vdso.o vdso/
> > > > >  obj-$(CONFIG_RISCV_MISALIGNED)       += traps_misaligned.o
> > > > >  obj-$(CONFIG_FPU)            += fpu.o
> > > > >  obj-$(CONFIG_RISCV_ISA_V)    += vector.o
> > > > > +obj-$(CONFIG_RISCV_ISA_V)    += kernel_mode_vector.o
> > > > >  obj-$(CONFIG_SMP)            += smpboot.o
> > > > >  obj-$(CONFIG_SMP)            += smp.o
> > > > >  obj-$(CONFIG_SMP)            += cpu_ops.o
> > > > > diff --git a/arch/riscv/kernel/kernel_mode_vector.c b/arch/riscv/kernel/kernel_mode_vector.c
> > > > > new file mode 100644
> > > > > index 000000000000..105147c7d2da
> > > > > --- /dev/null
> > > > > +++ b/arch/riscv/kernel/kernel_mode_vector.c
> > > > > @@ -0,0 +1,95 @@
> > > > > +// SPDX-License-Identifier: GPL-2.0-or-later
> > > > > +/*
> > > > > + * Copyright (C) 2012 ARM Ltd.
> > > > > + * Author: Catalin Marinas <catalin.marinas@arm.com>
> > > > > + * Copyright (C) 2017 Linaro Ltd. <ard.biesheuvel@linaro.org>
> > > > > + * Copyright (C) 2021 SiFive
> > > > > + */
> > > > > +#include <linux/compiler.h>
> > > > > +#include <linux/irqflags.h>
> > > > > +#include <linux/percpu.h>
> > > > > +#include <linux/preempt.h>
> > > > > +#include <linux/types.h>
> > > > > +
> > > > > +#include <asm/vector.h>
> > > > > +#include <asm/switch_to.h>
> > > > > +#include <asm/simd.h>
> > > > > +
> > > > > +/*
> > > > > + * Claim ownership of the CPU vector context for use by the calling context.
> > > > > + *
> > > > > + * The caller may freely manipulate the vector context metadata until
> > > > > + * put_cpu_vector_context() is called.
> > > > > + */
> > > > > +void get_cpu_vector_context(void)
> > > > > +{
> > > > > +     preempt_disable();
> > > > > +
> > > > > +     WARN_ON((riscv_v_ctx_cnt() & RISCV_KERNEL_MODE_V_MASK) != 0);
> > > > > +     riscv_v_ctx_cnt_add(RISCV_KERNEL_MODE_V);
> > > >
> > > > In our last conversation I thought we agreed that a bitwise operation
> > > > would be more appropriate then addition. You also mentioned allowing
> > > > this function to be called multiple times. Did something change?
> > >
> > > I am having the same discussion with Eric on this thread [1]. Using
> > > counter add/sub and mask with the bitmask provides the same overflow
> > > protection. It also helps us reuse the same mechanism for preempt_v
> > > and for allowing this function to be called multiple times. I have not
> > > done the second part because it is going to be very close to an idea
> > > of enabling V for the entire kernel. For example, it is possible to
> > > launch a kernel thread and wrap it with kernel_vector_*. If people
> > > feel ok about this then I will add this into v9. We will have to
> > > change the bitmap a little, and track context at trap entry/exit
> > > regardless of CONFIG_RISCV_ISA_V_PREEMPTIVE.
> > >
> > > - [1]: https://lore.kernel.org/all/20231222053014.GC52600@quark.localdomain/T/#m4f87d3c745853d518f96fb87a48c1d59e63b3d18
> > >
> > > Thanks,
> 
> Hey, I figured out a way to address the above problems, please wait for v9.
> 
> > > Andy
> >
> > Okay I understand now, it is a counter to know how many calls along the
> > chain have called get_cpu_vector_context. However, if it is not yet
> > supported to have nested calls to get_cpu_vector_context, then it should
> > be an error to call it more than once and not just a warning.
> 
> Do you suggest promoting WARN_ON to a BUG_ON?

Yes. I think that is more clear in this case.

> 
> >
> > - Charlie
> >
> 
> Thanks,
> Andy

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