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Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan , Jann Horn , Conor Dooley , linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, Zong Li Subject: Re: [PATCH v12 03/28] riscv: zicfiss / zicfilp enumeration Message-ID: References: <20250314-v5_user_cfi_series-v12-0-e51202b53138@rivosinc.com> <20250314-v5_user_cfi_series-v12-3-e51202b53138@rivosinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250409_074347_951090_80BA8D7F X-CRM114-Status: GOOD ( 17.93 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Apr 07, 2025 at 05:48:27PM +0200, Alexandre Ghiti wrote: > >On 14/03/2025 22:39, Deepak Gupta wrote: >>This patch adds support for detecting zicfiss and zicfilp. zicfiss and >>zicfilp stands for unprivleged integer spec extension for shadow stack >>and branch tracking on indirect branches, respectively. >> >>This patch looks for zicfiss and zicfilp in device tree and accordinlgy >>lights up bit in cpu feature bitmap. Furthermore this patch adds detection >>utility functions to return whether shadow stack or landing pads are >>supported by cpu. >> >>Reviewed-by: Zong Li >>Signed-off-by: Deepak Gupta >>--- >> arch/riscv/include/asm/cpufeature.h | 13 +++++++++++++ >> arch/riscv/include/asm/hwcap.h | 2 ++ >> arch/riscv/include/asm/processor.h | 1 + >> arch/riscv/kernel/cpufeature.c | 13 +++++++++++++ >> 4 files changed, 29 insertions(+) >> >>diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h >>index 569140d6e639..69007b8100ca 100644 >>--- a/arch/riscv/include/asm/cpufeature.h >>+++ b/arch/riscv/include/asm/cpufeature.h >>@@ -12,6 +12,7 @@ >> #include >> #include >> #include >>+#include >> #include >> #include >>@@ -137,4 +138,16 @@ static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsi >> return __riscv_isa_extension_available(hart_isa[cpu].isa, ext); >> } >>+static inline bool cpu_supports_shadow_stack(void) >>+{ >>+ return (IS_ENABLED(CONFIG_RISCV_USER_CFI) && >>+ riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICFISS)); > > >I would use riscv_has_extension_unlikely() instead of the cpu specific >variant, that would remove the need for #include . Unless >you have a good reason to do that? No I dont remember the reason. I'll fix it. When I am fixing it, and happpen to remember the reason. I'll post it. > > >>+} >>+ >>+static inline bool cpu_supports_indirect_br_lp_instr(void) >>+{ >>+ return (IS_ENABLED(CONFIG_RISCV_USER_CFI) && >>+ riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICFILP)); >>+} >>+ >> #endif >>diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h >>index 869da082252a..2dc4232bdb3e 100644 >>--- a/arch/riscv/include/asm/hwcap.h >>+++ b/arch/riscv/include/asm/hwcap.h >>@@ -100,6 +100,8 @@ >> #define RISCV_ISA_EXT_ZICCRSE 91 >> #define RISCV_ISA_EXT_SVADE 92 >> #define RISCV_ISA_EXT_SVADU 93 >>+#define RISCV_ISA_EXT_ZICFILP 94 >>+#define RISCV_ISA_EXT_ZICFISS 95 >> #define RISCV_ISA_EXT_XLINUXENVCFG 127 >>diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h >>index 5f56eb9d114a..e3aba3336e63 100644 >>--- a/arch/riscv/include/asm/processor.h >>+++ b/arch/riscv/include/asm/processor.h >>@@ -13,6 +13,7 @@ >> #include >> #include >>+#include >> #define arch_get_mmap_end(addr, len, flags) \ >> ({ \ >>diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c >>index c6ba750536c3..82065cc55822 100644 >>--- a/arch/riscv/kernel/cpufeature.c >>+++ b/arch/riscv/kernel/cpufeature.c >>@@ -150,6 +150,15 @@ static int riscv_ext_svadu_validate(const struct riscv_isa_ext_data *data, >> return 0; >> } >>+static int riscv_cfi_validate(const struct riscv_isa_ext_data *data, >>+ const unsigned long *isa_bitmap) >>+{ >>+ if (!IS_ENABLED(CONFIG_RISCV_USER_CFI)) >>+ return -EINVAL; >>+ >>+ return 0; >>+} >>+ >> static const unsigned int riscv_zk_bundled_exts[] = { >> RISCV_ISA_EXT_ZBKB, >> RISCV_ISA_EXT_ZBKC, >>@@ -333,6 +342,10 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { >> __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts, >> riscv_ext_zicboz_validate), >> __RISCV_ISA_EXT_DATA(ziccrse, RISCV_ISA_EXT_ZICCRSE), >>+ __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicfilp, RISCV_ISA_EXT_ZICFILP, riscv_xlinuxenvcfg_exts, >>+ riscv_cfi_validate), >>+ __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicfiss, RISCV_ISA_EXT_ZICFISS, riscv_xlinuxenvcfg_exts, >>+ riscv_cfi_validate), >> __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), >> __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND), >> __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), >> > >With the above comment fixed, you can add: > >Reviewed-by: Alexandre Ghiti > >Thanks, > >Alex > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv