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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, Feb 01, 2024 at 03:02:45PM +0100, Cl=E9ment L=E9ger wrote: > Some userspace applications (OpenJDK for instance) uses the free bits > in pointers to insert additional information for their own logic. > Currently they rely on parsing /proc/cpuinfo to obtain the current value > of virtual address used bits [1]. Exporting VA_BITS through hwprobe will > allow for a more stable interface to be used. mmap already supports this without a need for applications to know the underlying hardware. If a hint address is passed into mmap, it will never return an address that uses more bits than the hint address. I designed it that way so that something like this wasn't necessary. - Charlie > = > Link: https://github.com/openjdk/jdk/blob/master/src/hotspot/os_cpu/linux= _riscv/vm_version_linux_riscv.cpp#L171 [1] > Signed-off-by: Cl=E9ment L=E9ger > = > --- > Documentation/arch/riscv/hwprobe.rst | 3 +++ > arch/riscv/include/asm/hwprobe.h | 2 +- > arch/riscv/include/uapi/asm/hwprobe.h | 1 + > arch/riscv/kernel/sys_hwprobe.c | 3 +++ > 4 files changed, 8 insertions(+), 1 deletion(-) > = > diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/ri= scv/hwprobe.rst > index b2bcc9eed9aa..6f198c6ed4f0 100644 > --- a/Documentation/arch/riscv/hwprobe.rst > +++ b/Documentation/arch/riscv/hwprobe.rst > @@ -210,3 +210,6 @@ The following keys are defined: > = > * :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which > represents the size of the Zicboz block in bytes. > + > +* :c:macro:`RISCV_HWPROBE_KEY_VA_BITS`: An unsigned long which > + represent the number of bits used to store virtual addresses. > diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hw= probe.h > index 630507dff5ea..150a9877b0af 100644 > --- a/arch/riscv/include/asm/hwprobe.h > +++ b/arch/riscv/include/asm/hwprobe.h > @@ -8,7 +8,7 @@ > = > #include > = > -#define RISCV_HWPROBE_MAX_KEY 6 > +#define RISCV_HWPROBE_MAX_KEY 7 > = > static inline bool riscv_hwprobe_key_is_valid(__s64 key) > { > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/u= api/asm/hwprobe.h > index 9f2a8e3ff204..2a5006cddb7b 100644 > --- a/arch/riscv/include/uapi/asm/hwprobe.h > +++ b/arch/riscv/include/uapi/asm/hwprobe.h > @@ -67,6 +67,7 @@ struct riscv_hwprobe { > #define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0) > #define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0) > #define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6 > +#define RISCV_HWPROBE_KEY_VA_BITS 7 > /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ > = > /* Flags */ > diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwpr= obe.c > index a7c56b41efd2..328435836e36 100644 > --- a/arch/riscv/kernel/sys_hwprobe.c > +++ b/arch/riscv/kernel/sys_hwprobe.c > @@ -202,6 +202,9 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pa= ir, > if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOZ)) > pair->value =3D riscv_cboz_block_size; > break; > + case RISCV_HWPROBE_KEY_VA_BITS: > + pair->value =3D VA_BITS; > + break; > = > /* > * For forward compatibility, unknown keys don't fail the whole > -- = > 2.43.0 > = > = > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv