Re: [RFC PATCH 0/5] RISC-V: Add dynamic TSO support

From: Andrea Parri <parri.andrea@gmail.com>
To: Jonas Oberhauser <jonas.oberhauser@huaweicloud.com>
Cc: "Peter Zijlstra" <peterz@infradead.org>,
	"Christoph Muellner" <christoph.muellner@vrull.eu>,
	linux-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Andrew Morton" <akpm@linux-foundation.org>,
	"Shuah Khan" <shuah@kernel.org>,
	"Jonathan Corbet" <corbet@lwn.net>,
	"Anup Patel" <apatel@ventanamicro.com>,
	"Philipp Tomsich" <philipp.tomsich@vrull.eu>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Guo Ren" <guoren@kernel.org>,
	"Daniel Henrique Barboza" <dbarboza@ventanamicro.com>,
	"Conor Dooley" <conor.dooley@microchip.com>,
	"Björn Töpel" <bjorn@rivosinc.com>,
	"Alan Stern" <stern@rowland.harvard.edu>,
	"Will Deacon" <will@kernel.org>,
	"Daniel Lustig" <dlustig@nvidia.com>,
	"Brendan Sweeney" <turtwig@utexas.edu>,
	"Hans Boehm" <hboehm@google.com>,
	"Andrew Waterman" <andrew@sifive.com>
Subject: Re: [RFC PATCH 0/5] RISC-V: Add dynamic TSO support
Date: Thu, 8 Feb 2024 12:10:52 +0100	[thread overview]
Message-ID: <ZcS2vDZjQzDARefn@andrea> (raw)
In-Reply-To: <59da3e41-abb3-405a-8f98-c74bdf26935b@huaweicloud.com>

On Fri, Nov 24, 2023 at 12:04:09PM +0100, Jonas Oberhauser wrote:
> Unfortunately, at least last time I checked RISC-V still hadn't gotten such
> instructions.
> What they have is the *semantics* of the instructions, but no actual opcodes
> to encode them.
> I argued for them in the RISC-V memory group, but it was considered to be
> outside the scope of that group.

(Sorry for the late, late reply; just recalled this thread...)

That's right.  AFAICT, the discussion about the native load-acquire
and store-release instructions was revived somewhere last year within
the RVI community, culminating in the so called Zalasr-proposal [1];
Brendan, Hans and Andrew (+ Cc) might be able to provide more up-to-
date information about the status/plans for that proposal.

(Remark that RISC-V did introduce LR/SCs and AMOs instructions with
acquire/release semantics separately, cf. the so called A-extension.)

  Andrea

[1] https://github.com/mehnadnerd/riscv-zalasr

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