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Wysocki" , Len Brown , Paul Walmsley , Palmer Dabbelt , Albert Ou , Viresh Kumar , Conor Dooley , Andrew Jones , Atish Kumar Patra , Anup Patel Subject: Re: [PATCH v1 -next 0/3] RISC-V: ACPI: Enable CPPC based cpufreq support Message-ID: References: <20240208034414.22579-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240319_235438_162929_41702B0C X-CRM114-Status: GOOD ( 28.09 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, Mar 19, 2024 at 03:50:21PM +0530, Sunil V L wrote: > On Mon, Mar 18, 2024 at 07:27:34PM -0700, Drew Fustini wrote: > > On Mon, Mar 18, 2024 at 11:40:34AM -0700, Drew Fustini wrote: > > > On Thu, Feb 08, 2024 at 09:14:11AM +0530, Sunil V L wrote: > > > > This series enables the support for "Collaborative Processor Performance > > > > Control (CPPC) on ACPI based RISC-V platforms. It depends on the > > > > encoding of CPPC registers as defined in RISC-V FFH spec [2]. > > > > > > > > CPPC is described in the ACPI spec [1]. RISC-V FFH spec required to > > > > enable this, is available at [2]. > > > > > > > > [1] - https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html#collaborative-processor-performance-control > > > > [2] - https://github.com/riscv-non-isa/riscv-acpi-ffh/releases/download/v1.0.0/riscv-ffh.pdf > > > > > > > > The series is based on the LPI support series. > > > > Based-on: 20240118062930.245937-1-sunilvl@ventanamicro.com > > > > (https://lore.kernel.org/lkml/20240118062930.245937-1-sunilvl@ventanamicro.com/) > > > > > > Should the https://github.com/vlsunil/qemu/tree/lpi_exp branch also be > > > used for this CPPC series too? > > > > I noticed the ventanamicro qemu repo has a dev-upstream branch [1] which > > contains 4bb6ba4d0fb9 ("riscv/virt: acpi: Enable CPPC - _CPC and _PSD"). > > I've built that but I still see 'SBI CPPC extension NOT detected!!' in > > the Linux boot log. > > > > I'm using upstream opensbi. It seems that sbi_cppc_probe() fails because > > cppc_dev is not set. Nothing in the upstream opensbi repo seems to call > > sbi_cppc_set_device(), so I am uncertain how it is possible for it to > > work. Is there an opensbi branch I should be using? > > > > Thanks, > > Drew > > > > [1] https://github.com/ventanamicro/qemu/tree/dev-upstream > > Please use below branches for qemu and opensbi. These are just dummy > objects/interfaces added to test the kernel change which are otherwise > platform specific features. > > https://github.com/vlsunil/qemu/tree/lpi_cppc_exp > https://github.com/vlsunil/opensbi/tree/cppc_exp Thank you for providing those branches. The CPPC extension is now detected okay during boot but I see the following in the boot log [1]: [ 1.094707] cpufreq: cpufreq_online: ->get() failed Have you seen that too? This appears to be from the following in drivers/cpufreq/cpufreq.c 1500 if (cpufreq_driver->get && has_target()) { 1501 policy->cur = cpufreq_driver->get(policy->cpu); 1502 if (!policy->cur) { 1503 ret = -EIO; 1504 pr_err("%s: ->get() failed\n", __func__); 1505 goto out_destroy_policy; 1506 } 1507 } I'm not very familiar with the cpufreq code yet. My first thought is that maybe the get() function pointer isn't set correctly? thanks, drew [1] https://gist.github.com/pdp7/00ab047509d25871f87b3dc1b2445eaa _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv