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Tue, 16 Apr 2024 13:39:36 -0700 (PDT) Received: from ghost ([50.145.13.30]) by smtp.gmail.com with ESMTPSA id u22-20020a1709026e1600b001e2ba8605dfsm8797603plk.150.2024.04.16.13.39.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Apr 2024 13:39:36 -0700 (PDT) Date: Tue, 16 Apr 2024 13:39:33 -0700 From: Charlie Jenkins To: Conor Dooley Cc: Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Guo Ren , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Conor Dooley , Evan Green , =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= , Jonathan Corbet , Shuah Khan , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH v2 04/17] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree Message-ID: References: <20240415-dev-charlie-support_thead_vector_6_9-v2-0-c7d68c603268@rivosinc.com> <20240415-dev-charlie-support_thead_vector_6_9-v2-4-c7d68c603268@rivosinc.com> <20240416-scorer-easeful-4dae3c18465d@spud> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240416-scorer-easeful-4dae3c18465d@spud> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240416_133938_767648_D6D6E2D7 X-CRM114-Status: GOOD ( 20.74 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, Apr 16, 2024 at 04:28:19PM +0100, Conor Dooley wrote: > On Mon, Apr 15, 2024 at 09:12:01PM -0700, Charlie Jenkins wrote: > > The D1/D1s SoCs support xtheadvector which should be included in the > > devicetree. Also include vendorid for the cpu. > > > > Signed-off-by: Charlie Jenkins > > --- > > arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > > index 64c3c2e6cbe0..4788bb50afa2 100644 > > --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > > @@ -27,7 +27,8 @@ cpu0: cpu@0 { > > riscv,isa = "rv64imafdc"; > > riscv,isa-base = "rv64i"; > > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", > > - "zifencei", "zihpm"; > > + "zifencei", "zihpm", "xtheadvector"; > > > > + riscv,vendorid = <0x00000000 0x0000005b7>; > > Isn't this effectively useless given there's only one CPU here? > We also already know the vendor of the hart, because the compatible says > it is a "thead,c906" so this doesn't provide any new information. Yes, it was simply to provide an example of using this field to make it easier for somebody who wants to use it in the future. I can remove it if it's confusing. - Charlie > > > #cooling-cells = <2>; > > > > cpu0_intc: interrupt-controller { > > > > -- > > 2.44.0 > > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv