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Fri, 26 Apr 2024 13:34:23 -0700 (PDT) Received: from ghost ([2601:647:5700:6860:3b15:3aba:70a1:7ce9]) by smtp.gmail.com with ESMTPSA id fv3-20020a056a00618300b006eb3c3db4afsm15223011pfb.186.2024.04.26.13.34.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Apr 2024 13:34:22 -0700 (PDT) Date: Fri, 26 Apr 2024 13:34:19 -0700 From: Charlie Jenkins To: Conor Dooley Cc: Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Guo Ren , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Conor Dooley , Evan Green , =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= , Jonathan Corbet , Shuah Khan , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH v3 09/17] riscv: drivers: Convert xandespmu to use the vendor extension framework Message-ID: References: <20240420-dev-charlie-support_thead_vector_6_9-v3-0-67cff4271d1d@rivosinc.com> <20240420-dev-charlie-support_thead_vector_6_9-v3-9-67cff4271d1d@rivosinc.com> <20240426-venue-maximum-f78ac451b146@spud> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240426-venue-maximum-f78ac451b146@spud> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240426_133424_432575_30DDA21E X-CRM114-Status: GOOD ( 24.81 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, Apr 26, 2024 at 05:25:20PM +0100, Conor Dooley wrote: > On Sat, Apr 20, 2024 at 06:04:41PM -0700, Charlie Jenkins wrote: > > Migrate xandespmu out of riscv_isa_ext and into a new Andes-specific > > vendor namespace. > > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c > > index 8cbe6e5f9c39..84760ce61e03 100644 > > --- a/drivers/perf/riscv_pmu_sbi.c > > +++ b/drivers/perf/riscv_pmu_sbi.c > > @@ -24,6 +24,8 @@ > > #include > > #include > > #include > > +#include > > +#include > > > > #define ALT_SBI_PMU_OVERFLOW(__ovl) \ > > asm volatile(ALTERNATIVE_2( \ > > @@ -32,7 +34,7 @@ asm volatile(ALTERNATIVE_2( \ > > THEAD_VENDOR_ID, ERRATA_THEAD_PMU, \ > > CONFIG_ERRATA_THEAD_PMU, \ > > "csrr %0, " __stringify(ANDES_CSR_SCOUNTEROF), \ > > - 0, RISCV_ISA_EXT_XANDESPMU, \ > > + ANDES_VENDOR_ID, RISCV_ISA_VENDOR_EXT_XANDESPMU, \ > > CONFIG_ANDES_CUSTOM_PMU) \ > > : "=r" (__ovl) : \ > > : "memory") > > @@ -41,7 +43,7 @@ asm volatile(ALTERNATIVE_2( \ > > asm volatile(ALTERNATIVE( \ > > "csrc " __stringify(CSR_IP) ", %0\n\t", \ > > "csrc " __stringify(ANDES_CSR_SLIP) ", %0\n\t", \ > > - 0, RISCV_ISA_EXT_XANDESPMU, \ > > + ANDES_VENDOR_ID, RISCV_ISA_VENDOR_EXT_XANDESPMU, \ > > CONFIG_ANDES_CUSTOM_PMU) \ > > : : "r"(__irq_mask) \ > > : "memory") > > @@ -837,7 +839,7 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pde > > riscv_cached_mimpid(0) == 0) { > > riscv_pmu_irq_num = THEAD_C9XX_RV_IRQ_PMU; > > riscv_pmu_use_irq = true; > > - } else if (riscv_isa_extension_available(NULL, XANDESPMU) && > > + } else if (riscv_isa_vendor_extension_available(-1, XANDESPMU) && > > What's the rationale for this not using riscv_has_extension_unlikely()? > Happens once in probe so don't bother? I forget if we discussed it when > the code was added, but it would save us from the NULL/-1 syntax, > neither of which I think is a good interface. Doesn't look like something that was ever commented on in the series, but I may have missed it. I can change this to use the alternatives. This also wasn't supposed to be -1, it's supposed to be the id of the vendor. > > Also, I'd prob drop the "drivers" from $subject. > > I'll come back and look at the rest of this Monday, it's a sunny Friday > here and I've still got my devicetree patch queue to clear.. > - Charlie > Cheers, > Conor. > > > IS_ENABLED(CONFIG_ANDES_CUSTOM_PMU)) { > > riscv_pmu_irq_num = ANDES_SLI_CAUSE_BASE + ANDES_RV_IRQ_PMOVI; > > riscv_pmu_use_irq = true; > > > > -- > > 2.44.0 > > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv