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Sun, 05 May 2024 15:46:03 -0700 (PDT) Received: from andrea ([31.189.114.81]) by smtp.gmail.com with ESMTPSA id a25-20020a1709064a5900b00a59a9949ec9sm2188379ejv.118.2024.05.05.15.46.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 May 2024 15:46:02 -0700 (PDT) Date: Mon, 6 May 2024 00:45:58 +0200 From: Andrea Parri To: Puranjay Mohan Cc: Will Deacon , Peter Zijlstra , Boqun Feng , Mark Rutland , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, puranjay12@gmail.com Subject: Re: [PATCH] riscv/atomic.h: optimize ops with acquire/release ordering Message-ID: References: <20240505123340.38495-1-puranjay@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240505123340.38495-1-puranjay@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240505_154611_289090_C040DE51 X-CRM114-Status: GOOD ( 12.50 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hi Puranjay, On Sun, May 05, 2024 at 12:33:40PM +0000, Puranjay Mohan wrote: > Currently, atomic ops with acquire or release ordering are implemented > as atomic ops with relaxed ordering followed by or preceded by an > acquire fence or a release fence. > > Section 8.1 of the "The RISC-V Instruction Set Manual Volume I: > Unprivileged ISA", titled, "Specifying Ordering of Atomic Instructions" > says: > > | To provide more efficient support for release consistency [5], each > | atomic instruction has two bits, aq and rl, used to specify additional > | memory ordering constraints as viewed by other RISC-V harts. > > and > > | If only the aq bit is set, the atomic memory operation is treated as > | an acquire access. > | If only the rl bit is set, the atomic memory operation is treated as a > | release access. > > So, rather than using two instructions (relaxed atomic op + fence), use > a single atomic op instruction with acquire/release ordering. > > Example program: > > atomic_t cnt = ATOMIC_INIT(0); > atomic_fetch_add_acquire(1, &cnt); > atomic_fetch_add_release(1, &cnt); > > Before: > > amoadd.w a4,a5,(a4) // Atomic add with relaxed ordering > fence r,rw // Fence to force Acquire ordering > > fence rw,w // Fence to force Release ordering > amoadd.w a4,a5,(a4) // Atomic add with relaxed ordering > > After: > > amoadd.w.aq a4,a5,(a4) // Atomic add with Acquire ordering > > amoadd.w.rl a4,a5,(a4) // Atomic add with Release ordering > > Signed-off-by: Puranjay Mohan Your changes are effectively partially reverting: 5ce6c1f3535fa ("riscv/atomic: Strengthen implementations with fences") Can you please provide (and possibly include in the changelog of v2) a more thoughtful explanation for the correctness of such revert? (Anticipating a somewhat non-trivial analysis...) Have you tried your changes on some actual hardware? How did they perform? Anything worth mentioning (besides the mere instruction count)? Andrea _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv