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Wed, 08 May 2024 08:04:44 -0700 (PDT) Received: from andrea ([31.189.114.81]) by smtp.gmail.com with ESMTPSA id es26-20020a056402381a00b00572e2879500sm5484449edb.53.2024.05.08.08.04.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 May 2024 08:04:44 -0700 (PDT) Date: Wed, 8 May 2024 17:04:40 +0200 From: Andrea Parri To: Puranjay Mohan Cc: Daniel Lustig , Will Deacon , Peter Zijlstra , Boqun Feng , Mark Rutland , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH] riscv/atomic.h: optimize ops with acquire/release ordering Message-ID: References: <20240505123340.38495-1-puranjay@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240508_080448_287382_28847AA3 X-CRM114-Status: GOOD ( 18.36 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org > From my understanding of the current version of the RV memory model: > > .aq provides .aq -> all ordering > .rl provides all -> .rl ordering > and because this is RCsc variant of release consistency > .rl -> .aq > > which means > > R/W > amoswap.w.rl > amoswap.w.aq > R/W > > Should act as a full fence? R/W -> rl -> aq -> R/W Yes, hence the RCsc ("sc" for "sequential consistent") qualification. > So, I will do the following now: > > 1. Do some benchmarking on real hardware and find out how much overhead > these weak fences add. > 2. Study the LKMM and the RVWMO for the next few weeks/months or however > much time it takes me to confidently reason about things written in > these two models. > 3. Study the locking / related code of RISC-V to see what could break if > we change all these operations in accordance with "Code Porting and > Mapping Guidelines" of RISCV ISA. > 4. I will use the herd7 models of LKMM and RVWMO and see if everything > works as expected after these changes. > > > And If I am convinced after all this, I will send a patch to implement > "Code Porting and Mapping Guidelines" + provide performance numbers from > real hardware. > > Thanks for the detailed explainations and especially regarding how the > LKMM evolved. Sounds good! Thanks. Andrea _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv