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Wed, 08 May 2024 10:05:33 -0700 (PDT) Received: from ghost ([2601:647:5700:6860:1d01:8836:5e9d:e040]) by smtp.gmail.com with ESMTPSA id jx7-20020a170903138700b001e469386fddsm12124945plb.40.2024.05.08.10.05.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 May 2024 10:05:32 -0700 (PDT) Date: Wed, 8 May 2024 10:05:30 -0700 From: Charlie Jenkins To: Ben Dooks Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Song Liu , Xi Wang , =?iso-8859-1?Q?Bj=F6rn_T=F6pel?= , =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= , Jessica Clarke , Andy Chiu , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 3/8] riscv: Add PLATFORM_SUPPORTS_RISCV_ISA_SVNAPOT Kconfig option Message-ID: References: <20240507-compile_kernel_with_extensions-v2-0-722c21c328c6@rivosinc.com> <20240507-compile_kernel_with_extensions-v2-3-722c21c328c6@rivosinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240508_100555_888542_0F92DD8D X-CRM114-Status: GOOD ( 37.48 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, May 08, 2024 at 10:00:48AM +0100, Ben Dooks wrote: > On 08/05/2024 02:36, Charlie Jenkins wrote: > > The existing "RISCV_ISA_SVNAPOT" option is repurposed to be used to by > > kernel code to determine if either > > PLATFORM_MAY_SUPPORT_RISCV_ISA_SVNAPOT or > > PLATFORM_SUPPORTS_RISCV_ISA_SVNAPOT has been set. > > > > PLATFORM_MAY_SUPPORT_RISCV_ISA_SVNAPOT will check if the hardware > > supports Svnapot before using it, while > > PLATFORM_SUPPORTS_RISCV_ISA_SVNAPOT will assume that the hardware > > supports Svnapot. > > > > Signed-off-by: Charlie Jenkins > > --- > > arch/riscv/Kconfig | 19 ----------------- > > arch/riscv/Kconfig.isa | 44 ++++++++++++++++++++++++++++++++++++++++ > > arch/riscv/include/asm/pgtable.h | 3 ++- > > 3 files changed, 46 insertions(+), 20 deletions(-) > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > > index c2e9eded0a7d..3c1960e8cd7c 100644 > > --- a/arch/riscv/Kconfig > > +++ b/arch/riscv/Kconfig > > @@ -484,25 +484,6 @@ config RISCV_ALTERNATIVE_EARLY > > help > > Allows early patching of the kernel for special errata > > -config RISCV_ISA_SVNAPOT > > - bool "Svnapot extension support for supervisor mode NAPOT pages" > > - depends on 64BIT && MMU > > - depends on RISCV_ALTERNATIVE > > - default y > > - help > > - Add support for the Svnapot ISA-extension in the kernel when it > > - is detected at boot. > > - > > - The Svnapot extension is used to mark contiguous PTEs as a range > > - of contiguous virtual-to-physical translations for a naturally > > - aligned power-of-2 (NAPOT) granularity larger than the base 4KB page > > - size. When HUGETLBFS is also selected this option unconditionally > > - allocates some memory for each NAPOT page size supported by the kernel. > > - When optimizing for low memory consumption and for platforms without > > - the Svnapot extension, it may be better to say N here. > > - > > - If you don't know what to do here, say Y. > > - > > config RISCV_ISA_SVPBMT > > bool "Svpbmt extension support for supervisor mode page-based memory types" > > depends on 64BIT && MMU > > diff --git a/arch/riscv/Kconfig.isa b/arch/riscv/Kconfig.isa > > index 0663c98b5b17..37585bcd763e 100644 > > --- a/arch/riscv/Kconfig.isa > > +++ b/arch/riscv/Kconfig.isa > > @@ -124,3 +124,47 @@ config RISCV_ISA_V_PREEMPTIVE > > This config allows kernel to run SIMD without explicitly disable > > preemption. Enabling this config will result in higher memory > > consumption due to the allocation of per-task's kernel Vector context. > > + > > +config RISCV_ISA_SVNAPOT > > + bool > > + > > +choice > > + prompt "Svnapot extension support for supervisor mode NAPOT pages" > > + default PLATFORM_MAY_SUPPORT_RISCV_ISA_SVNAPOT > > + help > > + This selects the level of support for Svnapot in the Linux Kernel. > > + > > + The Svnapot extension is used to mark contiguous PTEs as a range > > + of contiguous virtual-to-physical translations for a naturally > > + aligned power-of-2 (NAPOT) granularity larger than the base 4KB page > > + size. When HUGETLBFS is also selected this option unconditionally > > + allocates some memory for each NAPOT page size supported by the kernel. > > + When optimizing for low memory consumption and for platforms without > > + the Svnapot extension, it may be better to prohibit Svnapot. > > + > > +config PROHIBIT_RISCV_ISA_SVNAPOT > > + bool "Prohibit Svnapot extension" > > + help > > + Regardless of if the platform supports Svnapot, prohibit the kernel > > + from using Svnapot. > > + > > +config PLATFORM_MAY_SUPPORT_RISCV_ISA_SVNAPOT > > + bool "Allow Svnapot extension if supported" > > + depends on 64BIT && MMU > > + depends on RISCV_ALTERNATIVE > > + select RISCV_ISA_SVNAPOT > > + help > > + Add support for the Svnapot ISA-extension in the kernel when it > > + is detected at boot. > > + > > +config PLATFORM_SUPPORTS_RISCV_ISA_SVNAPOT > > + bool "Emit Svnapot mappings when building Linux" > > + depends on 64BIT && MMU > > + depends on NONPORTABLE > > + select RISCV_ISA_SVNAPOT > > + help > > + Compile a kernel that assumes that the platform supports Svnapot. > > + This option produces a kernel that will not run on systems that do > > + not support Svnapot. > > + > > +endchoice > > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h > > index 6afd6bb4882e..432be9691b78 100644 > > --- a/arch/riscv/include/asm/pgtable.h > > +++ b/arch/riscv/include/asm/pgtable.h > > @@ -289,7 +289,8 @@ static inline pte_t pud_pte(pud_t pud) > > static __always_inline bool has_svnapot(void) > > { > > - return riscv_has_extension_likely(RISCV_ISA_EXT_SVNAPOT); > > + return IS_ENABLED(CONFIG_PLATFORM_SUPPORTS_RISCV_ISA_SVNAPOT) || > > + riscv_has_extension_likely(RISCV_ISA_EXT_SVNAPOT); > > could you add the IS_ENABLED(*) check into riscv_has_extension_likely > and other such functions? I wasn't sure how to support that. An option I was debating about this was fixing up riscv_has_extension_likely() so that it's a macro and SVNAPOT could be expanded to both CONFIG_PLATFORM_SUPPORTS_RISCV_ISA_SVNAPOT and RISCV_ISA_EXT_SVNAPOT. - Charlie > > > -- > Ben Dooks http://www.codethink.co.uk/ > Senior Engineer Codethink - Providing Genius > > https://www.codethink.co.uk/privacy.html > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv