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Sun, 02 Jun 2024 17:41:42 -0700 (PDT) Received: from andrea ([151.76.32.59]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57a6522d405sm470024a12.1.2024.06.02.17.41.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jun 2024 17:41:41 -0700 (PDT) Date: Mon, 3 Jun 2024 02:41:36 +0200 From: Andrea Parri To: Guo Ren Cc: Alexandre Ghiti , Alexandre Ghiti , Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Peter Zijlstra , Ingo Molnar , Will Deacon , Waiman Long , Boqun Feng , Arnd Bergmann , Leonardo Bras , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org Subject: Re: [PATCH 7/7] riscv: Add qspinlock support based on Zabha extension Message-ID: References: <20240528151052.313031-1-alexghiti@rivosinc.com> <20240528151052.313031-8-alexghiti@rivosinc.com> <39a9b28c-2792-45ce-a8c6-1703cab0f2de@ghiti.fr> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240602_174147_810691_3C1FA1B9 X-CRM114-Status: GOOD ( 10.39 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org > I looked at the riscv-unprivileged ppo section, seems RISC-V .rl -> > .aq has RCsc annotations. > ref: > Explicit Synchronization > 5. has an acquire annotation > 6. has a release annotation > 7. a and b both have RCsc annotations > > And for qspinlock: > unlock: > smp_store_release(&lock->locked, 0); > > lock: > if (likely(atomic_try_cmpxchg_acquire(&lock->val, &val, _Q_LOCKED_VAL))) > > If the hardware has Store-Release and CAS instructions, they all obey > Explicit Synchronization rules. Then RISC-V "UNLOCK+LOCK" pairs act as > a full barrier, right? Presuming you were thinking at CAS.aq (based on your previous remarks above), that all seems right to me. In fact, the (putative) Store.rl and an LR.aq would also do it (by the same/mentioned rules). Andrea _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv