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Thu, 06 Jun 2024 15:10:17 -0700 (PDT) Received: from ghost ([50.145.13.30]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-6de2017fc69sm1356840a12.17.2024.06.06.15.10.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jun 2024 15:10:16 -0700 (PDT) Date: Thu, 6 Jun 2024 15:10:13 -0700 From: Charlie Jenkins To: Conor Dooley Cc: Jesse Taube , linux-riscv@lists.infradead.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Evan Green , Andrew Jones , Xiao Wang , =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= , Andy Chiu , Greentime Hu , Heiko Stuebner , Guo Ren , =?iso-8859-1?Q?Bj=F6rn_T=F6pel?= , Costa Shulyupin , Andrew Morton , Baoquan He , Sami Tolvanen , Zong Li , Ben Dooks , Erick Archer , Vincent Chen , Joel Granados , linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/3] RISC-V: Add Zicclsm to cpufeature and hwprobe Message-ID: References: <20240606183215.416829-1-jesse@rivosinc.com> <20240606-acetone-whisking-af2ba796238f@spud> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240606-acetone-whisking-af2ba796238f@spud> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240606_151021_892970_6A6CA129 X-CRM114-Status: GOOD ( 30.80 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, Jun 06, 2024 at 07:43:52PM +0100, Conor Dooley wrote: > On Thu, Jun 06, 2024 at 02:32:13PM -0400, Jesse Taube wrote: > > > Zicclsm Misaligned loads and stores to main memory regions with both > > > the cacheability and coherence PMAs must be supported. > > > Note: > > > This introduces a new extension name for this feature. > > > This requires misaligned support for all regular load and store > > > instructions (including scalar and vector) but not AMOs or other > > > specialized forms of memory access. Even though mandated, misaligned > > > loads and stores might execute extremely slowly. Standard software > > > distributions should assume their existence only for correctness, > > > not for performance. > > > > Detecing zicclsm allows the kernel to report if the > > hardware supports misaligned accesses even if support wasn't probed. > > > > This is useful for usermode to know if vector misaligned accesses are > > supported. > > > > Signed-off-by: Jesse Taube > > --- > > arch/riscv/include/asm/hwcap.h | 1 + > > arch/riscv/include/uapi/asm/hwprobe.h | 1 + > > arch/riscv/kernel/cpufeature.c | 1 + > > arch/riscv/kernel/sys_hwprobe.c | 1 + > > 4 files changed, 4 insertions(+) > > > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > > index e17d0078a651..8c0d0b555a8e 100644 > > --- a/arch/riscv/include/asm/hwcap.h > > +++ b/arch/riscv/include/asm/hwcap.h > > @@ -81,6 +81,7 @@ > > #define RISCV_ISA_EXT_ZTSO 72 > > #define RISCV_ISA_EXT_ZACAS 73 > > #define RISCV_ISA_EXT_XANDESPMU 74 > > +#define RISCV_ISA_EXT_ZICCLSM 75 > > > > #define RISCV_ISA_EXT_XLINUXENVCFG 127 > > > > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h > > index 2902f68dc913..060212331a03 100644 > > --- a/arch/riscv/include/uapi/asm/hwprobe.h > > +++ b/arch/riscv/include/uapi/asm/hwprobe.h > > @@ -59,6 +59,7 @@ struct riscv_hwprobe { > > #define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33) > > #define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34) > > #define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35) > > +#define RISCV_HWPROBE_EXT_ZICCLSM (1ULL << 36) > > Missing an update to hwprobe.rst. > "RISCV_HWPROBE_EXT_ZIHINTPAUSE (1ULL << 36)" was also defined here in 6.10 so this key needs to be bumped down one. - Charlie > > #define RISCV_HWPROBE_KEY_CPUPERF_0 5 > > #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) > > #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > > index 3ed2359eae35..863c708f2f2e 100644 > > --- a/arch/riscv/kernel/cpufeature.c > > +++ b/arch/riscv/kernel/cpufeature.c > > @@ -305,6 +305,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > > __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), > > __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), > > __RISCV_ISA_EXT_DATA(xandespmu, RISCV_ISA_EXT_XANDESPMU), > > + __RISCV_ISA_EXT_DATA(zicclsm, RISCV_ISA_EXT_ZICCLSM), > > Please read the ordering comment above this structure! > Also, you're missing dt-binding documentation for the extension. > > > }; > > > > const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext); > > diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c > > index 8cae41a502dd..b286b73e763e 100644 > > --- a/arch/riscv/kernel/sys_hwprobe.c > > +++ b/arch/riscv/kernel/sys_hwprobe.c > > @@ -125,6 +125,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, > > EXT_KEY(ZVKT); > > EXT_KEY(ZVFH); > > EXT_KEY(ZVFHMIN); > > + EXT_KEY(ZICCLSM); > > Order looks off here too, I think this should be added in in the same > order as to riscv_isa_ext, although the requirement isn't hard here, > just that adding to the end of a list means it's annoying to check for > what's missing. > > Thanks, > Conor. > > > } > > > > if (has_fpu()) { > > -- > > 2.43.0 > > > > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv