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Fri, 07 Jun 2024 11:51:10 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f6ea2d17c5sm7512365ad.46.2024.06.07.11.51.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jun 2024 11:51:09 -0700 (PDT) Date: Fri, 7 Jun 2024 11:51:07 -0700 From: Deepak Gupta To: Conor Dooley Cc: Alexandre Ghiti , Jesse Taube , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Alexandre Ghiti , Palmer Dabbelt , Albert Ou , =?iso-8859-1?Q?Bj=F6rn_T=F6pel?= , Paul Walmsley , Nathan Chancellor , Nick Desaulniers , Masahiro Yamada , =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= , Atish Patra Subject: Re: [PATCH v0] RISC-V: Use Zkr to seed KASLR base address Message-ID: References: <20240531162327.2436962-1-jesse@rivosinc.com> <20240531-uselessly-spied-262ecf44e694@spud> <20240603-stinking-roster-cfad46696ae5@spud> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240603-stinking-roster-cfad46696ae5@spud> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240607_115115_323719_9681907F X-CRM114-Status: GOOD ( 27.82 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Jun 03, 2024 at 01:47:40PM +0100, Conor Dooley wrote: >On Mon, Jun 03, 2024 at 11:14:49AM +0200, Alexandre Ghiti wrote: >> Hi Conor, >> >> On 31/05/2024 19:31, Conor Dooley wrote: >> > On Fri, May 31, 2024 at 12:23:27PM -0400, Jesse Taube wrote: >> > > Dectect the Zkr extension and use it to seed the kernel base address. >> > > >> > > Detection of the extension can not be done in the typical fashion, as >> > > this is very early in the boot process. Instead, add a trap handler >> > > and run it to see if the extension is present. >> > You can't rely on the lack of a trap meaning that Zkr is present unless >> > you know that the platform implements Ssstrict. The CSR with that number >> > could do anything if not Ssstrict compliant, so this approach gets a >> > nak from me. Unfortunately, Ssstrict doesn't provide a way to detect >> > it, so you're stuck with getting that information from firmware. >> >> >> FYI, this patch is my idea, so I'm the one to blame here :) >> >> >> > >> > For DT systems, you can actually parse the DT in the pi, we do it to get >> > the kaslr seed if present, so you can actually check for Zkr. With ACPI >> > I have no idea how you can get that information, I amn't an ACPI-ist. >> >> >> I took a look at how to access ACPI tables this early when implementing the >> Zabha/Zacas patches, but it seems not possible. >> >> But I'll look into this more, this is not the first time we need the >> extensions list very early and since we have no way to detect the presence >> of an extension at runtime, something needs to be done. > >Aye, having remembered that reading CSR_SEED could have side-effects on a >system with non-conforming extensions, it'd be good to see if we can >actually do this via detection on ACPI - especially for some other >extensions that we may need to turn on very early (I forget which ones we >talked about this before for). I didn't arm64 do anything with ACPI in the >pi code, is the code arch/x86/boot/compressed run at an equivilent-ish point >in boot? cc: +Clement and Atish I don't know all the details but on first glance it seems like instead of ACPI, may be FWFT is a better place for discovery ? https://lists.riscv.org/g/tech-prs/topic/patch_v12_add_firmware/106479571 Supervisor could query if Sstrict is implemented and then it can check for lack of trap on CSR_SEED or straight-away check for presence of Zkr. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv