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Mon, 10 Jun 2024 09:38:10 -0700 (PDT) Received: from ghost ([2601:647:5700:6860:129d:83bc:830b:8292]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-6deb62efb66sm5525307a12.12.2024.06.10.09.38.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jun 2024 09:38:09 -0700 (PDT) Date: Mon, 10 Jun 2024 09:38:06 -0700 From: Charlie Jenkins To: Conor Dooley Cc: Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH 02/13] dt-bindings: thead: add a vlen register length property Message-ID: References: <20240609-xtheadvector-v1-0-3fe591d7f109@rivosinc.com> <20240609-xtheadvector-v1-2-3fe591d7f109@rivosinc.com> <20240610-unaltered-crazily-5b63e224d633@spud> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240610-unaltered-crazily-5b63e224d633@spud> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240610_093813_016022_6208B628 X-CRM114-Status: GOOD ( 24.86 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Jun 10, 2024 at 05:29:23PM +0100, Conor Dooley wrote: > On Sun, Jun 09, 2024 at 09:45:07PM -0700, Charlie Jenkins wrote: > > Add a property analogous to the vlenb CSR so that software can detect > > the vector length of each CPU prior to it being brought online. > > Currently software has to assume that the vector length read from the > > boot CPU applies to all possible CPUs. On T-Head CPUs implementing > > pre-ratification vector, reading the th.vlenb CSR may produce an illegal > > instruction trap, so this property is required on such systems. > > > > Signed-off-by: Charlie Jenkins > > --- > > Documentation/devicetree/bindings/riscv/thead.yaml | 7 +++++++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/riscv/thead.yaml b/Documentation/devicetree/bindings/riscv/thead.yaml > > index 301912dcd290..5e578df36ac5 100644 > > --- a/Documentation/devicetree/bindings/riscv/thead.yaml > > +++ b/Documentation/devicetree/bindings/riscv/thead.yaml > > @@ -28,6 +28,13 @@ properties: > > - const: sipeed,lichee-module-4a > > - const: thead,th1520 > > > > +thead,vlenb: > > This needs to move back into cpus.yaml, this file documents root node > compatibles (boards and socs etc) and is not for CPUs. If you want to > restrict this to T-Head CPUs only, it must be done in cpus.yaml with > a conditional `if: not: ... then: properties: thead,vlenb: false`. > > Please test your bindings. Now that I know `make dt_binding_check` exists I will use that in the future! - Charlie > > Thanks, > Conor. > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + description: > > + VLEN/8, the vector register length in bytes. This property is required in > > + systems where the vector register length is not identical on all harts, or > > + the vlenb CSR is not available. > > + > > additionalProperties: true > > > > ... > > > > -- > > 2.44.0 > > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv