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Wed, 19 Jun 2024 10:04:07 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c7c989b35bsm1446583a91.46.2024.06.19.10.04.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Jun 2024 10:04:07 -0700 (PDT) Date: Wed, 19 Jun 2024 10:04:05 -0700 From: Deepak Gupta To: Jisheng Zhang Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Samuel Holland , Clement Leger , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 3/6] riscv: convert bottom half of exception handling to C Message-ID: References: <20240616170553.2832-1-jszhang@kernel.org> <20240616170553.2832-4-jszhang@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240616170553.2832-4-jszhang@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240619_100408_746959_1CA05A7C X-CRM114-Status: GOOD ( 11.55 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Jun 17, 2024 at 01:05:50AM +0800, Jisheng Zhang wrote: >For readability, maintainability and future scalability, convert the >bottom half of the exception handling to C. > >Mostly the assembly code is converted to C in a relatively >straightforward manner. > >However, there are two modifications I need to mention: > >1. the CSR_CAUSE reg reading and saving is moved to the C code >because we need the cause to dispatch the exception handling, >if we keep the cause reading and saving, we either pass it to >do_traps() via. 2nd param or get it from pt_regs which an extra >memory load is needed, I don't like any of the two solutions becase >the exception handling sits in hot code path, every instruction >matters. CC: Clement. I think its better to save away cause in pt_regs prior to calling `do_traps`. Once control is transferred to C code in `do_traps`, another trap can happen. It's a problem anyways today without CPU support. Although with Ssdbltrp [1] extension and it kernel support [2] for it, I expect asm code would clear up `SDT` bit in mstatus. Whenever `Ssdbltrp` lands, I think `do_traps` should expect nesting of traps and thus cause should be saved away before it gets control so that safely traps can be nested. [1] - https://github.com/riscv/riscv-double-trap/releases/download/v1.0-rc1/riscv-double-trap.pdf [2] - https://lore.kernel.org/all/20240418133916.1442471-1-cleger@rivosinc.com/ > >2.To cope with SIFIVE_CIP_453 errata, it looks like we don't need >alternative mechanism any more after the asm->c convertion. Just >replace the excp_vect_table two entries. > >Signed-off-by: Jisheng Zhang _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv