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Tue, 09 Jul 2024 13:29:45 -0700 (PDT) Received: from ghost ([50.145.13.30]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-77d5f0ab0bfsm1810102a12.1.2024.07.09.13.29.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jul 2024 13:29:45 -0700 (PDT) Date: Tue, 9 Jul 2024 13:29:42 -0700 From: Charlie Jenkins To: Conor Dooley Cc: Xiao Wang , Alexandre Ghiti , paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, atishp@atishpatra.org, anup@brainfault.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] drivers/perf: riscv: Remove redundant macro check Message-ID: References: <20240708121224.1148154-1-xiao.w.wang@intel.com> <20240708-wildcard-denim-12de7fae795b@spud> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240708-wildcard-denim-12de7fae795b@spud> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240709_132946_865040_170F2FF2 X-CRM114-Status: GOOD ( 22.89 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Jul 08, 2024 at 01:22:11PM +0100, Conor Dooley wrote: > On Mon, Jul 08, 2024 at 08:12:24PM +0800, Xiao Wang wrote: > > The macro CONFIG_RISCV_PMU must have been defined when riscv_pmu.c gets > > compiled, so this patch removes the redundant check. > > Did you investigate why this define was added? Why do you think that it > is redundant, rather than checking the incorrect config option? This file is only compiled with CONFIG_RISCV_PMU: # drivers/perf/Makefile obj-$(CONFIG_RISCV_PMU) += riscv_pmu.o So having this check does seem redundant. I am copying Alex as it looks like he wrote this. - Charlie > > Cheers, > Conor. > > > > > Signed-off-by: Xiao Wang > > --- > > drivers/perf/riscv_pmu.c | 2 -- > > 1 file changed, 2 deletions(-) > > > > diff --git a/drivers/perf/riscv_pmu.c b/drivers/perf/riscv_pmu.c > > index 0a02e85a8951..7644147d50b4 100644 > > --- a/drivers/perf/riscv_pmu.c > > +++ b/drivers/perf/riscv_pmu.c > > @@ -39,7 +39,6 @@ void arch_perf_update_userpage(struct perf_event *event, > > userpg->cap_user_time_short = 0; > > userpg->cap_user_rdpmc = riscv_perf_user_access(event); > > > > -#ifdef CONFIG_RISCV_PMU > > /* > > * The counters are 64-bit but the priv spec doesn't mandate all the > > * bits to be implemented: that's why, counter width can vary based on > > @@ -47,7 +46,6 @@ void arch_perf_update_userpage(struct perf_event *event, > > */ > > if (userpg->cap_user_rdpmc) > > userpg->pmc_width = to_riscv_pmu(event->pmu)->ctr_get_width(event->hw.idx) + 1; > > -#endif > > > > do { > > rd = sched_clock_read_begin(&seq); > > -- > > 2.25.1 > > > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv