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Mon, 01 Jul 2024 21:34:19 -0700 (PDT) Received: from ghost ([2601:647:5700:6860:a569:328b:99ad:ce17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-72c6d3efeddsm5826997a12.88.2024.07.01.21.34.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jul 2024 21:34:18 -0700 (PDT) Date: Mon, 1 Jul 2024 21:34:16 -0700 From: Charlie Jenkins To: zhouquan@iscas.ac.cn Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, oleg@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, andy.chiu@sifive.com, shuah@kernel.org Subject: Re: [PATCH v1 1/2] riscv: Expose orig_a0 in the user_regs_struct structure Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240701_213420_824125_2A834470 X-CRM114-Status: GOOD ( 19.83 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, Jun 27, 2024 at 11:02:46AM +0800, zhouquan@iscas.ac.cn wrote: > From: Quan Zhou > > Expose orig_a0 to userspace to ensure that users can modify > the actual value of `a0` in the traced process through the > ptrace(PTRACE_SETREGSET, ...) path. > > The addition of orig_a0 also requires the following adjustments: > 1) Adjust the position of orig_a0 in pt_regs to ensure correct copying. > 2) MAX_REG_OFFSET should match the new bottom of pt_regs. > > Suggested-by: Charlie Jenkins > Signed-off-by: Quan Zhou > --- > arch/riscv/include/asm/ptrace.h | 7 ++++--- > arch/riscv/include/uapi/asm/ptrace.h | 2 ++ > 2 files changed, 6 insertions(+), 3 deletions(-) > > diff --git a/arch/riscv/include/asm/ptrace.h b/arch/riscv/include/asm/ptrace.h > index b5b0adcc85c1..380cf54c1f3d 100644 > --- a/arch/riscv/include/asm/ptrace.h > +++ b/arch/riscv/include/asm/ptrace.h > @@ -12,6 +12,7 @@ > > #ifndef __ASSEMBLY__ > > +/* MAX_REG_OFFSET should match the bottom of pt_regs */ > struct pt_regs { > unsigned long epc; > unsigned long ra; > @@ -45,12 +46,12 @@ struct pt_regs { > unsigned long t4; > unsigned long t5; > unsigned long t6; > + /* a0 value before the syscall */ > + unsigned long orig_a0; > /* Supervisor/Machine CSRs */ > unsigned long status; > unsigned long badaddr; > unsigned long cause; > - /* a0 value before the syscall */ > - unsigned long orig_a0; > }; > > #define PTRACE_SYSEMU 0x1f > @@ -64,7 +65,7 @@ struct pt_regs { > > #define user_mode(regs) (((regs)->status & SR_PP) == 0) > > -#define MAX_REG_OFFSET offsetof(struct pt_regs, orig_a0) > +#define MAX_REG_OFFSET offsetof(struct pt_regs, cause) > > /* Helpers for working with the instruction pointer */ > static inline unsigned long instruction_pointer(struct pt_regs *regs) > diff --git a/arch/riscv/include/uapi/asm/ptrace.h b/arch/riscv/include/uapi/asm/ptrace.h > index a38268b19c3d..3e37f80cb3e8 100644 > --- a/arch/riscv/include/uapi/asm/ptrace.h > +++ b/arch/riscv/include/uapi/asm/ptrace.h > @@ -54,6 +54,8 @@ struct user_regs_struct { > unsigned long t4; > unsigned long t5; > unsigned long t6; > + /* a0 value before the syscall */ > + unsigned long orig_a0; > }; > > struct __riscv_f_ext_state { > -- > 2.34.1 > Thank you! Reviewed-by: Charlie Jenkins _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv