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R. Silva" , Erick Archer , Joel Granados , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v4 7/7] RISC-V: hwprobe: Document unaligned vector perf key Message-ID: References: <20240711215846.834365-1-jesse@rivosinc.com> <20240711215846.834365-8-jesse@rivosinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240711215846.834365-8-jesse@rivosinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240711_152316_161269_E85A58BA X-CRM114-Status: GOOD ( 19.37 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, Jul 11, 2024 at 05:58:46PM -0400, Jesse Taube wrote: > Document key for reporting the speed of unaligned vector accesses. > The descriptions are the same as the scalar equivalent values. > > Signed-off-by: Jesse Taube > --- > V1 -> V2: > - New patch > V2 -> V3: > - Specify access width > V3 -> V4: > - Clarify we're talking about byte accesses using vector registers > - Spell out _VECTOR_ in macros > --- > Documentation/arch/riscv/hwprobe.rst | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst > index 78acd37b6477..f83a13dc4cbc 100644 > --- a/Documentation/arch/riscv/hwprobe.rst > +++ b/Documentation/arch/riscv/hwprobe.rst > @@ -238,3 +238,19 @@ The following keys are defined: > > * :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which > represents the size of the Zicboz block in bytes. > + > +* :c:macro:`RISCV_HWPROBE_KEY_VECTOR_MISALIGNED_PERF`: An enum value describing the > + performance of misaligned vector accesses on the selected set of processors. > + > + * :c:macro:`RISCV_HWPROBE_VECTOR_MISALIGNED_UNKNOWN`: The performance of misaligned > + vector accesses is unknown. > + > + * :c:macro:`RISCV_HWPROBE_VECTOR_MISALIGNED_SLOW`: 32-bit misaligned accesses using vector > + registers are slower than the equivalent quantity of byte accesses via vector registers. > + Misaligned accesses may be supported directly in hardware, or trapped and emulated by software. > + > + * :c:macro:`RISCV_HWPROBE_VECTOR_MISALIGNED_FAST`: 32-bit misaligned accesses using vector > + registers are faster than the equivalent quantity of byte accesses via vector registers. > + > + * :c:macro:`RISCV_HWPROBE_VECTOR_MISALIGNED_UNSUPPORTED`: Misaligned vector accesses are > + not supported at all and will generate a misaligned address fault. > -- > 2.45.2 > Reviewed-by: Charlie Jenkins _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv