[PATCH v3 1/1] riscv: dts: thead: add basic spi node

Kanak Shilledar
2024-07-05T09:36:00Z

created spi0 node with fixed clock. the spi0 node
uses synopsis designware driver and has the following
compatible "snps,dw-apb-ssi". the spi0 node is connected
to a SPI NOR flash pad which is left unpopulated on the back
side of the board.

Acked-by: Drew Fustini <drew@pdp7.com>
Signed-off-by: Kanak Shilledar <kanakshilledar@gmail.com>
---
Changes in v3:
- Changed the position of "spi" to come after "serial" in
aliases for both the boards.
- Added Acked-by tag.
Changes in v2:
- Separated from a single patch file.
---
.../boot/dts/thead/th1520-beaglev-ahead.dts | 9 +++++++++
.../boot/dts/thead/th1520-lichee-module-4a.dtsi | 4 ++++
.../riscv/boot/dts/thead/th1520-lichee-pi-4a.dts | 5 +++++
arch/riscv/boot/dts/thead/th1520.dtsi | 16 ++++++++++++++++
4 files changed, 34 insertions(+)

diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
index d9b4de9e4757..b4d2e1d69bdb 100644
--- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
+++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
@@ -23,6 +23,7 @@ aliases {
serial3 = &uart3;
serial4 = &uart4;
serial5 = &uart5;
+ spi0 = &spi0;
};

chosen {
@@ -52,6 +53,10 @@ &sdhci_clk {
clock-frequency = <198000000>;
};

+&spi_clk {
+ clock-frequency = <396000000>;
+};
+
&uart_sclk {
clock-frequency = <100000000>;
};
@@ -79,3 +84,7 @@ &sdio0 {
&uart0 {
status = "okay";
};
+
+&spi0 {
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
index 1365d3a512a3..6939bd36560c 100644
--- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
@@ -33,6 +33,10 @@ &sdhci_clk {
clock-frequency = <198000000>;
};

+&spi_clk {
+ clock-frequency = <396000000>;
+};
+
&uart_sclk {
clock-frequency = <100000000>;
};
diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
index 9a3884a73e13..7738d2895c5a 100644
--- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
+++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
@@ -20,6 +20,7 @@ aliases {
serial3 = &uart3;
serial4 = &uart4;
serial5 = &uart5;
+ spi0 = &spi0;
};

chosen {
@@ -30,3 +31,7 @@ chosen {
&uart0 {
status = "okay";
};
+
+&spi0 {
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index d2fa25839012..f962de663e7e 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -140,6 +140,12 @@ apb_clk: apb-clk-clock {
#clock-cells = <0>;
};

+ spi_clk: spi-clock {
+ compatible = "fixed-clock";
+ clock-output-names = "spi_clk";
+ #clock-cells = <0>;
+ };
+
uart_sclk: uart-sclk-clock {
compatible = "fixed-clock";
clock-output-names = "uart_sclk";
@@ -183,6 +189,16 @@ clint: timer@ffdc000000 {
<&cpu3_intc 3>, <&cpu3_intc 7>;
};

+ spi0: spi@ffe700c000 {
+ compatible = "thead,th1520-spi", "snps,dw-apb-ssi";
+ reg = <0xff 0xe700c000 0x0 0x1000>;
+ interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&spi_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
uart0: serial@ffe7014000 {
compatible = "snps,dw-apb-uart";
reg = <0xff 0xe7014000 0x0 0x100>;
--
2.45.2