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Wed, 31 Jul 2024 18:10:58 -0700 (PDT) Received: from ghost ([50.145.13.30]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70ead8a3aa8sm10522229b3a.210.2024.07.31.18.10.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jul 2024 18:10:58 -0700 (PDT) Date: Wed, 31 Jul 2024 18:10:55 -0700 From: Charlie Jenkins To: =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Andrea Parri , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH 1/2] tools: Add riscv barrier implementation Message-ID: References: <20240729-optimize_ring_buffer_read_riscv-v1-0-6bbc0f2434ee@rivosinc.com> <20240729-optimize_ring_buffer_read_riscv-v1-1-6bbc0f2434ee@rivosinc.com> <28d780da-4f43-4db5-8e1b-c66bb9973cd1@rivosinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <28d780da-4f43-4db5-8e1b-c66bb9973cd1@rivosinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240731_181100_787133_5D1DE5BA X-CRM114-Status: GOOD ( 22.63 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, Jul 30, 2024 at 10:59:52AM +0200, Cl=E9ment L=E9ger wrote: > = > = > On 29/07/2024 22:50, Charlie Jenkins wrote: > > Many of the other architectures use their custom barrier implmentations. > = > Hi Charlie, > = > Typo: implmentations -> implementations Thank you! I will fix that. - Charlie > = > > Use the barrier code from the kernel sources to optimize barriers in > > tools. > > = > > Signed-off-by: Charlie Jenkins > > --- > > tools/arch/riscv/include/asm/barrier.h | 39 ++++++++++++++++++++++++++= ++++++++ > > tools/arch/riscv/include/asm/fence.h | 13 ++++++++++++ > > tools/include/asm/barrier.h | 2 ++ > > 3 files changed, 54 insertions(+) > > = > > diff --git a/tools/arch/riscv/include/asm/barrier.h b/tools/arch/riscv/= include/asm/barrier.h > > new file mode 100644 > > index 000000000000..6997f197086d > > --- /dev/null > > +++ b/tools/arch/riscv/include/asm/barrier.h > > @@ -0,0 +1,39 @@ > > +/* SPDX-License-Identifier: GPL-2.0-only */ > > +/* > > + * Copied from the kernel sources to tools/arch/riscv: > > + * > > + * Copyright (C) 2012 ARM Ltd. > > + * Copyright (C) 2013 Regents of the University of California > > + * Copyright (C) 2017 SiFive > > + */ > > + > > +#ifndef _TOOLS_LINUX_ASM_RISCV_BARRIER_H > > +#define _TOOLS_LINUX_ASM_RISCV_BARRIER_H > > + > > +#include > > +#include > > + > > +/* These barriers need to enforce ordering on both devices and memory.= */ > > +#define mb() RISCV_FENCE(iorw, iorw) > > +#define rmb() RISCV_FENCE(ir, ir) > > +#define wmb() RISCV_FENCE(ow, ow) > > + > > +/* These barriers do not need to enforce ordering on devices, just mem= ory. */ > > +#define smp_mb() RISCV_FENCE(rw, rw) > > +#define smp_rmb() RISCV_FENCE(r, r) > > +#define smp_wmb() RISCV_FENCE(w, w) > > + > > +#define smp_store_release(p, v) \ > > +do { \ > > + RISCV_FENCE(rw, w); \ > > + WRITE_ONCE(*p, v); \ > > +} while (0) > > + > > +#define smp_load_acquire(p) \ > > +({ \ > > + typeof(*p) ___p1 =3D READ_ONCE(*p); \ > > + RISCV_FENCE(r, rw); \ > > + ___p1; \ > > +}) > > + > > +#endif /* _TOOLS_LINUX_ASM_RISCV_BARRIER_H */ > > diff --git a/tools/arch/riscv/include/asm/fence.h b/tools/arch/riscv/in= clude/asm/fence.h > > new file mode 100644 > > index 000000000000..37860e86771d > > --- /dev/null > > +++ b/tools/arch/riscv/include/asm/fence.h > > @@ -0,0 +1,13 @@ > > +/* SPDX-License-Identifier: GPL-2.0-only */ > > +/* > > + * Copied from the kernel sources to tools/arch/riscv: > > + */ > > + > > +#ifndef _ASM_RISCV_FENCE_H > > +#define _ASM_RISCV_FENCE_H > > + > > +#define RISCV_FENCE_ASM(p, s) "\tfence " #p "," #s "\n" > > +#define RISCV_FENCE(p, s) \ > > + ({ __asm__ __volatile__ (RISCV_FENCE_ASM(p, s) : : : "memory"); }) > > + > > +#endif /* _ASM_RISCV_FENCE_H */ > > diff --git a/tools/include/asm/barrier.h b/tools/include/asm/barrier.h > > index 8d378c57cb01..0c21678ac5e6 100644 > > --- a/tools/include/asm/barrier.h > > +++ b/tools/include/asm/barrier.h > > @@ -8,6 +8,8 @@ > > #include "../../arch/arm64/include/asm/barrier.h" > > #elif defined(__powerpc__) > > #include "../../arch/powerpc/include/asm/barrier.h" > > +#elif defined(__riscv) > > +#include "../../arch/riscv/include/asm/barrier.h" > > #elif defined(__s390__) > > #include "../../arch/s390/include/asm/barrier.h" > > #elif defined(__sh__) > > = > = > Can not really tell for that part except it seems ok to me as well. > Andrea might be a better candidate to add its Rb. > = > Thanks, > = > Cl=E9ment _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv