[PATCH 0/2] riscv: Fix race conditions in PR_RISCV_SET_ICACHE_FLUSH_CTX

Charlie Jenkins
2024-08-13T23:28:47Z

There are two race conditions possible with
PR_RISCV_SET_ICACHE_FLUSH_CTX. The first one can be seen by enabling
DEBUG_PREEMPT and using this prctl which will warn with BUG: using
smp_processor_id() in preemptible. This can be fixed by disabling
preemption during this prctl handling. Another race condition is present
when the mm->context.icache_stale_mask is changed by a thread while a
different thread in the same mm context is between switch_mm() and
switch_to() during a context switch.

Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
---
Charlie Jenkins (2):
riscv: Disable preemption while handling PR_RISCV_CTX_SW_FENCEI_OFF
riscv: Eagerly flush in flush_icache_deferred()

arch/riscv/include/asm/switch_to.h | 19 ++++++++++++++++---
arch/riscv/mm/cacheflush.c | 13 +++++++------
arch/riscv/mm/context.c | 6 +-----
3 files changed, 24 insertions(+), 14 deletions(-)
---
base-commit: 7c626ce4bae1ac14f60076d00eafe71af30450ba
change-id: 20240812-fix_fencei_optimization-3f81ac200505
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- Charlie