From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DB82FC52D7C for ; Thu, 15 Aug 2024 17:01:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=sTixcWak3LLKOqGDxrW2JZvvk8r+fKk5ZwJu4vxbmm0=; b=oRwbQV6jphQNCI QyHNUQXOpMR4J+FLWr+R0w4WTrKBTPsqRlAo9Mx0SOQQ9FmbdXjlExdMY8fNcVUMVGzc83iJLbCJp ha9lJaF+1Gp6eonBWxrB5mlaYZTMr8FNKgwFZoS6Xux3oxf8X8yJx6Oxjs7ToFIQ8JigxiIFkMc46 4RVSXAqCrkC5znvr2HtNfx9u0Fc5qq3UTgzepJxY+aQn+CjNqeOYQaMTrEn9/qFY+1mFKP34DVpdk Xaz2nOdHhYvZR60/9mN0QZAfx0TtExWf/NCoFvdgd7WUApy6ubH0mnJ27JaBandwvM50zbic5GHEQ qkRot9rTVmV4P3/6XFjA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sedqW-0000000AaOj-2KKj; Thu, 15 Aug 2024 17:01:08 +0000 Received: from sin.source.kernel.org ([145.40.73.55]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sedpr-0000000AaG7-0W2m; Thu, 15 Aug 2024 17:00:28 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id 0D0D8CE1D1D; Thu, 15 Aug 2024 17:00:24 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7AED9C32786; Thu, 15 Aug 2024 17:00:17 +0000 (UTC) Date: Thu, 15 Aug 2024 18:00:15 +0100 From: Catalin Marinas To: Mark Brown Cc: Will Deacon , Jonathan Corbet , Andrew Morton , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Arnd Bergmann , Oleg Nesterov , Eric Biederman , Shuah Khan , "Rick P. Edgecombe" , Deepak Gupta , Ard Biesheuvel , Szabolcs Nagy , Kees Cook , "H.J. Lu" , Paul Walmsley , Palmer Dabbelt , Albert Ou , Florian Weimer , Christian Brauner , Thiago Jung Bauermann , Ross Burton , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-fsdevel@vger.kernel.org, linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH v10 04/40] arm64: Document boot requirements for Guarded Control Stacks Message-ID: References: <20240801-arm64-gcs-v10-0-699e2bd2190b@kernel.org> <20240801-arm64-gcs-v10-4-699e2bd2190b@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240801-arm64-gcs-v10-4-699e2bd2190b@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240815_100027_360513_37D01926 X-CRM114-Status: GOOD ( 12.15 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, Aug 01, 2024 at 01:06:31PM +0100, Mark Brown wrote: > + - If EL2 is present: > + > + - GCSCR_EL2 must be initialised to 0. > + > + - If the kernel is entered at EL1 and EL2 is present: > + > + - GCSCR_EL1 must be initialised to 0. > + > + - GCSCRE0_EL1 must be initialised to 0. Currently booting.rst doesn't list *_EL1 registers to be initialised when the kernel is entered at EL1, that would usually be the responsibility of EL1. The exception is some bits in SCTLR_EL1 around not entering with the MMU and caches enabled. But here I think it makes sense to add these GCS registers since if some random bits are set, they can affect kernels (and user apps) that don't have GCS support. Don't we need HCRX_EL2.GCSEn to be set when entered at EL1? -- Catalin _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv