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Mon, 19 Aug 2024 11:11:35 -0700 (PDT) Received: from ghost ([50.145.13.30]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7127add7cc8sm6847892b3a.36.2024.08.19.11.11.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2024 11:11:35 -0700 (PDT) Date: Mon, 19 Aug 2024 11:11:33 -0700 From: Charlie Jenkins To: Jesse Taube Cc: linux-riscv@lists.infradead.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= , Conor Dooley , Evan Green , Andrew Jones , linux-kernel@vger.kernel.org Subject: Re: [PATCH v1] RISC-V: hwprobe: Use BIT macro to avoid warnings Message-ID: References: <20240819180443.1774641-1-jesse@rivosinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240819180443.1774641-1-jesse@rivosinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240819_111137_290836_4DDB672B X-CRM114-Status: GOOD ( 16.20 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Aug 19, 2024 at 02:04:43PM -0400, Jesse Taube wrote: > In uapi/asm/hwprobe.h file, (1 << N) is used to define the bit feild "field" not "feild" > this causes checkpatch to warn. Use BIT(N) and BIT_ULL(N) to avoid The grammar is slightly odd here, I think replacing "this" with "which" makes the sentence less awkward. > warnings. > > Signed-off-by: Jesse Taube > --- > arch/riscv/include/uapi/asm/hwprobe.h | 102 +++++++++++++------------- > 1 file changed, 51 insertions(+), 51 deletions(-) > > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h > index b706c8e47b02..d0874ff2fd37 100644 > --- a/arch/riscv/include/uapi/asm/hwprobe.h > +++ b/arch/riscv/include/uapi/asm/hwprobe.h > @@ -21,57 +21,57 @@ struct riscv_hwprobe { > #define RISCV_HWPROBE_KEY_MARCHID 1 > #define RISCV_HWPROBE_KEY_MIMPID 2 > #define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3 > -#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0) > +#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA BIT_ULL(0) > #define RISCV_HWPROBE_KEY_IMA_EXT_0 4 > -#define RISCV_HWPROBE_IMA_FD (1 << 0) > -#define RISCV_HWPROBE_IMA_C (1 << 1) > -#define RISCV_HWPROBE_IMA_V (1 << 2) > -#define RISCV_HWPROBE_EXT_ZBA (1 << 3) > -#define RISCV_HWPROBE_EXT_ZBB (1 << 4) > -#define RISCV_HWPROBE_EXT_ZBS (1 << 5) > -#define RISCV_HWPROBE_EXT_ZICBOZ (1 << 6) > -#define RISCV_HWPROBE_EXT_ZBC (1 << 7) > -#define RISCV_HWPROBE_EXT_ZBKB (1 << 8) > -#define RISCV_HWPROBE_EXT_ZBKC (1 << 9) > -#define RISCV_HWPROBE_EXT_ZBKX (1 << 10) > -#define RISCV_HWPROBE_EXT_ZKND (1 << 11) > -#define RISCV_HWPROBE_EXT_ZKNE (1 << 12) > -#define RISCV_HWPROBE_EXT_ZKNH (1 << 13) > -#define RISCV_HWPROBE_EXT_ZKSED (1 << 14) > -#define RISCV_HWPROBE_EXT_ZKSH (1 << 15) > -#define RISCV_HWPROBE_EXT_ZKT (1 << 16) > -#define RISCV_HWPROBE_EXT_ZVBB (1 << 17) > -#define RISCV_HWPROBE_EXT_ZVBC (1 << 18) > -#define RISCV_HWPROBE_EXT_ZVKB (1 << 19) > -#define RISCV_HWPROBE_EXT_ZVKG (1 << 20) > -#define RISCV_HWPROBE_EXT_ZVKNED (1 << 21) > -#define RISCV_HWPROBE_EXT_ZVKNHA (1 << 22) > -#define RISCV_HWPROBE_EXT_ZVKNHB (1 << 23) > -#define RISCV_HWPROBE_EXT_ZVKSED (1 << 24) > -#define RISCV_HWPROBE_EXT_ZVKSH (1 << 25) > -#define RISCV_HWPROBE_EXT_ZVKT (1 << 26) > -#define RISCV_HWPROBE_EXT_ZFH (1 << 27) > -#define RISCV_HWPROBE_EXT_ZFHMIN (1 << 28) > -#define RISCV_HWPROBE_EXT_ZIHINTNTL (1 << 29) > -#define RISCV_HWPROBE_EXT_ZVFH (1 << 30) > -#define RISCV_HWPROBE_EXT_ZVFHMIN (1ULL << 31) > -#define RISCV_HWPROBE_EXT_ZFA (1ULL << 32) > -#define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33) > -#define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34) > -#define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35) > -#define RISCV_HWPROBE_EXT_ZIHINTPAUSE (1ULL << 36) > -#define RISCV_HWPROBE_EXT_ZVE32X (1ULL << 37) > -#define RISCV_HWPROBE_EXT_ZVE32F (1ULL << 38) > -#define RISCV_HWPROBE_EXT_ZVE64X (1ULL << 39) > -#define RISCV_HWPROBE_EXT_ZVE64F (1ULL << 40) > -#define RISCV_HWPROBE_EXT_ZVE64D (1ULL << 41) > -#define RISCV_HWPROBE_EXT_ZIMOP (1ULL << 42) > -#define RISCV_HWPROBE_EXT_ZCA (1ULL << 43) > -#define RISCV_HWPROBE_EXT_ZCB (1ULL << 44) > -#define RISCV_HWPROBE_EXT_ZCD (1ULL << 45) > -#define RISCV_HWPROBE_EXT_ZCF (1ULL << 46) > -#define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 47) > -#define RISCV_HWPROBE_EXT_ZAWRS (1ULL << 48) > +#define RISCV_HWPROBE_IMA_FD BIT_ULL(0) > +#define RISCV_HWPROBE_IMA_C BIT_ULL(1) > +#define RISCV_HWPROBE_IMA_V BIT_ULL(2) > +#define RISCV_HWPROBE_EXT_ZBA BIT_ULL(3) > +#define RISCV_HWPROBE_EXT_ZBB BIT_ULL(4) > +#define RISCV_HWPROBE_EXT_ZBS BIT_ULL(5) > +#define RISCV_HWPROBE_EXT_ZICBOZ BIT_ULL(6) > +#define RISCV_HWPROBE_EXT_ZBC BIT_ULL(7) > +#define RISCV_HWPROBE_EXT_ZBKB BIT_ULL(8) > +#define RISCV_HWPROBE_EXT_ZBKC BIT_ULL(9) > +#define RISCV_HWPROBE_EXT_ZBKX BIT_ULL(10) > +#define RISCV_HWPROBE_EXT_ZKND BIT_ULL(11) > +#define RISCV_HWPROBE_EXT_ZKNE BIT_ULL(12) > +#define RISCV_HWPROBE_EXT_ZKNH BIT_ULL(13) > +#define RISCV_HWPROBE_EXT_ZKSED BIT_ULL(14) > +#define RISCV_HWPROBE_EXT_ZKSH BIT_ULL(15) > +#define RISCV_HWPROBE_EXT_ZKT BIT_ULL(16) > +#define RISCV_HWPROBE_EXT_ZVBB BIT_ULL(17) > +#define RISCV_HWPROBE_EXT_ZVBC BIT_ULL(18) > +#define RISCV_HWPROBE_EXT_ZVKB BIT_ULL(19) > +#define RISCV_HWPROBE_EXT_ZVKG BIT_ULL(20) > +#define RISCV_HWPROBE_EXT_ZVKNED BIT_ULL(21) > +#define RISCV_HWPROBE_EXT_ZVKNHA BIT_ULL(22) > +#define RISCV_HWPROBE_EXT_ZVKNHB BIT_ULL(23) > +#define RISCV_HWPROBE_EXT_ZVKSED BIT_ULL(24) > +#define RISCV_HWPROBE_EXT_ZVKSH BIT_ULL(25) > +#define RISCV_HWPROBE_EXT_ZVKT BIT_ULL(26) > +#define RISCV_HWPROBE_EXT_ZFH BIT_ULL(27) > +#define RISCV_HWPROBE_EXT_ZFHMIN BIT_ULL(28) > +#define RISCV_HWPROBE_EXT_ZIHINTNTL BIT_ULL(29) > +#define RISCV_HWPROBE_EXT_ZVFH BIT_ULL(30) > +#define RISCV_HWPROBE_EXT_ZVFHMIN BIT_ULL(31) > +#define RISCV_HWPROBE_EXT_ZFA BIT_ULL(32) > +#define RISCV_HWPROBE_EXT_ZTSO BIT_ULL(33) > +#define RISCV_HWPROBE_EXT_ZACAS BIT_ULL(34) > +#define RISCV_HWPROBE_EXT_ZICOND BIT_ULL(35) > +#define RISCV_HWPROBE_EXT_ZIHINTPAUSE BIT_ULL(36) > +#define RISCV_HWPROBE_EXT_ZVE32X BIT_ULL(37) > +#define RISCV_HWPROBE_EXT_ZVE32F BIT_ULL(38) > +#define RISCV_HWPROBE_EXT_ZVE64X BIT_ULL(39) > +#define RISCV_HWPROBE_EXT_ZVE64F BIT_ULL(40) > +#define RISCV_HWPROBE_EXT_ZVE64D BIT_ULL(41) > +#define RISCV_HWPROBE_EXT_ZIMOP BIT_ULL(42) > +#define RISCV_HWPROBE_EXT_ZCA BIT_ULL(43) > +#define RISCV_HWPROBE_EXT_ZCB BIT_ULL(44) > +#define RISCV_HWPROBE_EXT_ZCD BIT_ULL(45) > +#define RISCV_HWPROBE_EXT_ZCF BIT_ULL(46) > +#define RISCV_HWPROBE_EXT_ZCMOP BIT_ULL(47) > +#define RISCV_HWPROBE_EXT_ZAWRS BIT_ULL(48) > #define RISCV_HWPROBE_KEY_CPUPERF_0 5 > #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) > #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) > @@ -85,6 +85,6 @@ struct riscv_hwprobe { > /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ > > /* Flags */ > -#define RISCV_HWPROBE_WHICH_CPUS (1 << 0) > +#define RISCV_HWPROBE_WHICH_CPUS BIT(0) > > #endif > -- > 2.45.2 > Thanks for doing this. It will be nice to not get this checkpatch warning anymore. Reviewed-by: Charlie Jenkins Tested-by: Charlie Jenkins _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv