From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 30F36E7C4C2 for ; Wed, 4 Oct 2023 14:18:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=WSl1tl0BKRBEU0n8tWU5Qzxe03/rq6jTprD8E1jgYKw=; b=axle3XJGtdzsRe QCk1tv8Av+RKXTO9XX59hs18z3aYZNt2SwAUK4RjiPzzB9s9uypRb+aXJZ9+tVY4g5pCv+PS1hik3 CV/Sp9hvKqa/LpTktnPsSqNy1uy0OzGqMxcDHiRunXeV6G1X8QKpkKIN0CzplVcJR/3R2HveJFCK2 +23e+BtNBI4Jd9VxPdRhcG+VWGBe19U8n3T35Lh7aWCmXnZBP8yGZcwmwYnag/F+5ct4vgdkgGhbW W5q/rOBFWS0e5KUhsHH9CxjOq87YdX2MULL4I0Y1wxvK6wOGvTafDTiyX8W3rcfplrWnIESndYHJR Ff/Av+CzRkIDPHWAdncA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qo2hs-000Cjc-01; Wed, 04 Oct 2023 14:18:32 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qo2hp-000Chv-0O for linux-riscv@lists.infradead.org; Wed, 04 Oct 2023 14:18:31 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6C5C7DA7; Wed, 4 Oct 2023 07:19:06 -0700 (PDT) Received: from [10.1.196.40] (e121345-lin.cambridge.arm.com [10.1.196.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8454B3F59C; Wed, 4 Oct 2023 07:18:24 -0700 (PDT) Message-ID: Date: Wed, 4 Oct 2023 15:18:23 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux aarch64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH 0/6] RISC-V: Add eMMC support for TH1520 boards Content-Language: en-GB To: Icenowy Zheng , "Lad, Prabhakar" , Jisheng Zhang Cc: Drew Fustini , Christoph Hellwig , Lad Prabhakar , Robert Nelson , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Adrian Hunter , Guo Ren , Fu Wei , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Jason Kridner , Xi Ruoyao , Han Gao , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= , Alexandre Ghiti , Linux-MM References: <20230921-th1520-mmc-v1-0-49f76c274fb3@baylibre.com> From: Robin Murphy In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231004_071829_251037_F5B0B4FA X-CRM114-Status: GOOD ( 15.99 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 04/10/2023 3:02 pm, Icenowy Zheng wrote: [...] >>>> I believe commit 484861e09f3e ("soc: renesas: Kconfig: Select the >>>> required configs for RZ/Five SoC") can cause regression on all >>>> non-dma-coherent riscv platforms with generic defconfig. This is >>>> a common issue. The logic here is: generic riscv defconfig >>>> selects >>>> ARCH_R9A07G043 which selects DMA_GLOBAL_POOL, which assumes all >>>> non-dma-coherent riscv platforms have a dma global pool, this >>>> assumption >>>> seems not correct. And I believe DMA_GLOBAL_POOL should not be >>>> selected by ARCH_SOCFAMILIY, instead, only ARCH under some >>>> specific >>>> conditions can select it globaly, for example NOMMU ARM and so >>>> on. >>>> >>>> Since this is a regression, what's proper fix? any suggestion is >>>> appreciated. >> >> I think the answer is to not select DMA_GLOBAL_POOL, since that is >> only > > Well I think for RISC-V, it's not NOMMU only but applicable for every > core that does not support Svpbmt or vendor-specific alternatives, > because the original RISC-V priv spec does not define memory attributes > in page table entries. > > For the Renesas/Andes case I think a pool is set by OpenSBI with > vendor-specific M-mode facility and then passed in DT, and the S-mode > (which MMU is enabled in) just sees fixed memory attributes, in this > case I think DMA_GLOBAL_POOL is needed. Oh wow, is that really a thing? In that case, either you just can't support this platform in a multi-platform kernel, or someone needs to do some fiddly work in dma-direct to a) introduce the notion of an optional global pool, and b) make it somehow cope with DMA_DIRECT_REMAP being enabled but non-functional. Thanks, Robin. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv