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Thu, 22 May 2025 01:20:18 -0700 (PDT) Received: from cyan-mbp ([136.226.240.168]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-231d4adca4asm104828005ad.78.2025.05.22.01.20.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 May 2025 01:20:17 -0700 (PDT) Date: Thu, 22 May 2025 16:20:13 +0800 From: Cyan Yang To: Geert Uytterhoeven Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, corbet@lwn.net, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, samuel.holland@sifive.com, linux-doc@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 02/12] riscv: Add SiFive xsfvqmaccdod and xsfvqmaccqoq vendor extensions Message-ID: References: <20250516030310.16950-1-cyan.yang@sifive.com> <20250516030310.16950-3-cyan.yang@sifive.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250522_012019_317263_BF78A8F0 X-CRM114-Status: GOOD ( 30.09 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, May 20, 2025 at 11:26:39AM +0200, Geert Uytterhoeven wrote: > Hi Cyan, > > On Fri, 16 May 2025 at 05:07, Cyan Yang wrote: > > Add SiFive vendor extension support to the kernel with the target of > > "xsfvqmaccdod" and "xsfvqmaccqoq". > > > > Signed-off-by: Cyan Yang > > Thanks for your patch, which is now commit 2d147d77ae6e96c1 ("riscv: > Add SiFive xsfvqmaccdod and xsfvqmaccqoq vendor extensions") > in riscv/for-next. > > > --- a/arch/riscv/Kconfig.vendor > > +++ b/arch/riscv/Kconfig.vendor > > @@ -16,6 +16,19 @@ config RISCV_ISA_VENDOR_EXT_ANDES > > If you don't know what to do here, say Y. > > endmenu > > > > +menu "SiFive" > > +config RISCV_ISA_VENDOR_EXT_SIFIVE > > + bool "SiFive vendor extension support" > > + select RISCV_ISA_VENDOR_EXT > > + default y > > I guess this has no dependency on ARCH_SIFIVE and does not default > to ARCH_SIFIVE because this extension can be present on non-Sifive > SoCs, too? > > Probably I should have asked this when the other RISCV_ISA_VENDOR_EXT_* > were introduced, but at least for ANDES I already know the answer. > Yes, you are right. ARCH_SIFIVE enables support for SiFive SoC platform. RISCV_ISA_VENDOR_EXT_SIFIVE enables support for SiFive vendor extensions, which are not limited to the SiFive SoC platform. > > + help > > + Say N here if you want to disable all SiFive vendor extension > > + support. This will cause any SiFive vendor extensions that are > > + requested by hardware probing to be ignored. > > + > > + If you don't know what to do here, say Y. > > +endmenu > > + > > menu "T-Head" > > config RISCV_ISA_VENDOR_EXT_THEAD > > bool "T-Head vendor extension support" > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds Regards, Cyan _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv